View AT89LP52-20AU_2779458.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

features ? 8-bit microcontroller compatible with 8051 products ? enhanced 8051 architecture ? single clock cycle per byte fetch ? 12 clock per machine cy cle compatibility mode ? up to 20 mips throughput at 20 mhz clock frequency ? fully static operation: 0 hz to 20 mhz ? on-chip 2-cycle hardware multiplier ? 256 x 8 internal ram ? external data/program memory interface ? dual data pointers ? 4-level interrupt priority ? nonvolatile program and data memory ? 4k/8k bytes of in-system progra mmable (isp) flash program memory ? 256 bytes of flash data memory ? 256-byte user signature array ? endurance: 10,000 write/erase cycles ? serial interface for program downloading ? 64-byte fast page programming mode ? 3-level program memory lo ck for software security ? in-application programming of program memory ? peripheral features ? three 16-bit timer/counte rs with clock out modes ? enhanced uart ? automatic address recognition ? framing error detection ? spi and twi emulation modes ? programmable watchdog timer with software reset and prescaler ? special microcontroller features ? brown-out detection and power-on reset with power-off flag ? selectable polarity external reset pin ? low power idle and power-down modes ? interrupt recovery from power-down mode ? internal 1.8432 mhz auxiliary oscillator ? i/o and packages ? up to 36 programmable i/o lines ? green (pb/halide-free) packages ? 40-lead pdip ? 44-lead tqfp/plcc ? 44-pad vqfn/mlf ? configurable port modes (per 8-bit port) ? quasi-bidirectional (80c51 style) ? input-only (tristate) ? push-pull cmos output ? open-drain ? operating conditions ? 2.4v to 5.5v v cc voltage range ?-40 c to 85c temperature range ? 0 to 20 mhz @ 2.4v?5.5v ? 0 to 25 mhz @ 4.5v?5.5v 8-bit microcontroller with 4k/8k bytes in-system programmable flash at89lp51 at89lp52 preliminary 3709c?micro?5/11
2 3709c?micro?5/11 at89lp51/52 - preliminary 1. pin configurations 1.1 40-lead pdip 1.2 44-lead tqfp 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 15 16 17 18 19 20 40 3 9 3 8 3 7 3 6 3 5 3 4 33 3 2 3 1 3 0 29 28 27 26 25 24 2 3 22 21 (t2) p1.0 (t2 ex) p1.1 p1.2 p1. 3 p1.4 (mosi) p1.5 (miso) p1.6 (sck) p1.7 rst (rxd) p 3 .0 (txd) p 3 .1 (int0) p 3 .2 (int1) p 3 . 3 (t0) p 3 .4 (t1) p 3 .5 (wr) p 3 .6 (rd) p 3 .7 (xtal2) p4.1 (xtal1) p4.0 gnd vcc p0.0 (ad0) p0.1 (ad1) p0.2 (ad2) p0. 3 (ad 3 ) p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) pol p4.2 (ale) p4. 3 (psen) p2.7 (a15) p2.6 (a14) p2.5 (a1 3 ) p2.4 (a12) p2. 3 (a11) p2.2 (a10) p2.1 (a9) p2.0 (a8) 1 2 3 4 5 6 7 8 9 10 11 33 3 2 3 1 3 0 29 28 27 26 25 24 2 3 44 4 3 42 41 40 3 9 3 8 3 7 3 6 3 5 3 4 12 1 3 14 15 16 17 18 19 20 21 22 (mosi) p1.5 (miso) p1.6 (sck) p1.7 rst (rxd) p 3 .0 *nc (txd) p 3 .1 (int0) p 3 .2 (int1) p 3 . 3 (t0) p 3 .4 (t1) p 3 .5 p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) pol *nc p4.4 (ale) p4.5 (psen) p2.7 (a15) p2.6 (a14) p2.5 (a1 3 ) p1.4 p1. 3 p1.2 p1.1 (t2 ex) p1.0 (t2) *nc vcc p0.0 (ad0) p0.1 (ad1) p0.2 (ad2) p0. 3 (ad 3 ) (wr) p 3 .6 (rd) p 3 .7 (xtal2) p4.7 (xtal1) p4.6 gnd *nc (a8) p2.0 (a9) p2.1 (a10) p2.2 (a11) p2. 3 (a12) p2.4
3 3709c?micro?5/11 at89lp51/52 - preliminary 1.3 44-lead plcc 1.4 44-pad vqfn/qfn/mlf 7 8 9 10 11 12 1 3 14 15 16 17 3 9 3 8 3 7 3 6 3 5 3 4 33 3 2 3 1 3 0 29 (mosi) p1.5 (miso) p1.6 (sck) p1.7 rst (rxd) p 3 .0 *nc (txd) p 3 .1 (int0) p 3 .2 (int1) p 3 . 3 (t0) p 3 .4 (t1) p 3 .5 p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) pol *nc p4.4 (ale) p4.5 (psen) p2.7 (a15) p2.6 (a14) p2.5 (a1 3 ) 6 5 4 3 2 1 44 4 3 42 41 40 18 19 20 21 22 2 3 24 25 26 27 28 (wr) p 3 .6 (rd) p 3 .7 (xtal2) p4.7 (xtal1) p4.6 gnd *nc (a8) p2.0 (a9) p2.1 (a10) p2.2 (a11) p2. 3 (a12) p2.4 p1.4 p1. 3 p1.2 p1.1 (t2 ex) p1.0 (t2) *nc vcc p0.0 (ad0) p0.1 (ad1) p0.2 (ad2) p0. 3 (ad 3 ) 1 2 3 4 5 6 7 8 9 10 11 33 3 2 3 1 3 0 29 28 27 26 25 24 2 3 44 4 3 42 41 40 3 9 3 8 3 7 3 6 3 5 3 4 12 1 3 14 15 16 17 18 19 20 21 22 bottom pad should be soldered to ground note: mosi/p1.5 miso/p1.6 sck/p1.7 rst rxd/p 3 .0 *nc txd/p 3 .1 int0/p 3 .2 int1/p 3 . 3 t0/p 3 .4 t1/p 3 .5 p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 pol *nc p4.4/ale p4.5/psen p2.7/a15 p2.6/a14 p2.5/a1 3 wr/p 3 .6 rd/p 3 .7 xtal2/p4.7 xtal1/p4.6 gnd *nc a8/p2.0 a9/p2.1 a10/p2.2 a11/p2. 3 a12/p2.4 p1.4 p1. 3 p1.2 p1.1/t2ex p1.0/t2 *nc vdd p0.0/ad0 p0.1/ad1 p0.2/ad2 p0. 3 /ad 3
4 3709c?micro?5/11 at89lp51/52 - preliminary 1.5 pin description table 1-1. at 8 9lp51/52 pin de s cription pin number symbol type description tqfp plcc pdip vqfn 1761p1.5 i/o i/o p1.5 : i/o port 1 b it 5. mosi : s pi m as ter-o u t/ s l a ve-in. in uart s pi mode thi s pin i s a n o u tp u t. d u ring in- s y s tem progr a mming, thi s pin i s a n inp u t. 2 8 72p1.6 i/o i/o p1.6 : i/o port 1 b it 6. miso : s pi m as ter-in/ s l a ve-o u t. in uart s pi mode thi s pin i s a n inp u t. d u ring in- s y s tem progr a mming, thi s pin i s a n o u tp u t. 39 8 3p1.7 i/o i/o p1.7 : i/o port 1 b it 7. sck : s pi clock. in uart s pi mode thi s pin i s a n o u tp u t. d u ring in- s y s tem progr a mming, thi s pin i s a n inp u t. 4109 4 r s t i/o rst : extern a l re s et inp u t (re s et pol a rity depend s on pol pin. s ee ?extern a l re s et? on p a ge 33. ). the r s t pin c a n o u tp u t a p u l s e when the intern a l w a tchdog re s et i s a ctive. 511105p3.0 i/o i p3.0 : i/o port 3 b it 0. rxd : s eri a l port receiver inp u t. 6 12 6 nc not intern a lly connected 713117p3.1 i/o o p3.1 : i/o port 3 b it 1. txd : s eri a l port tr a n s mitter o u tp u t. 8 14 12 8 p3.2 i/o i p3.2 : i/o port 3 b it 2. int0 : extern a l interr u pt 0 inp u t or timer 0 g a te inp u t. 915139p3.3 i/o i p3.3 : i/o port 3 b it 3. int1 : extern a l interr u pt 1 inp u t or timer 1 g a te inp u t 10 16 14 10 p3.4 i/o i/o p3.4 : i/o port 3 b it 4. t1 : timer/co u nter 0 extern a l inp u t or o u tp u t. 11 17 15 1 p3.5 i/o i/o p3.5 : i/o port 3 b it 5. t1 : timer/co u nter 1 extern a l inp u t or o u tp u t. 12 1 8 16 12 p3.6 i/o o p3.6 : i/o port 3 b it 6. wr : extern a l memory interf a ce write s tro b e ( a ctive-low). 13 19 17 13 p3.7 i/o o p3.7 : i/o port 3 b it 7. rd : extern a l memory interf a ce re a d s tro b e ( a ctive-low). 14 20 1 8 14 p4.7 i/o o p4.7 : i/o port 4 b it 7. xtal2 : o u tp u t from inverting o s cill a tor a mplifier. it m a y b e us ed as a port pin if the intern a l rc o s cill a tor or extern a l clock i s s elected as the clock s o u rce. 15 21 19 15 p4.6 i/o i p4.6 : i/o port 4 b it 6. xtal1 : inp u t to the inverting o s cill a tor a mplifier a nd intern a l clock gener a tion circ u it s . it m a y b e us ed as a port pin if the intern a l rc o s cill a tor i s s elected as the clock s o u rce. 16 22 20 16 gnd i gro u nd 17 23 17 nc not intern a lly connected 1 8 24 21 1 8 p2.0 i/o o p2.0 : i/o port 2 b it 0. a8 : extern a l memory interf a ce addre ss b it 8 . 19 25 22 19 p2.1 i/o o p2.1 : i/o port 2 b it 1. a9 : extern a l memory interf a ce addre ss b it 9. 20 26 23 20 p2.1 i/o o p2.2 : i/o port 2 b it 2. a10 : extern a l memory interf a ce addre ss b it 10.
5 3709c?micro?5/11 at89lp51/52 - preliminary 21 27 24 21 p2.3 i/o o p2.3 : i/o port 2 b it 3. a11 : extern a l memory interf a ce addre ss b it 11. 22 2 8 25 22 p2.4 i/o o p2.4 : i/o port 2 b it 5. a12 : extern a l memory interf a ce addre ss b it 12. 23 29 26 23 p2.5 i/o o p2.5 : i/o port 2 b it 5. a13 : extern a l memory interf a ce addre ss b it 13. 24 30 27 24 p2.6 i/o o p2.6 : i/o port 2 b it 6. a14 : extern a l memory interf a ce addre ss b it 14. 25 31 2 8 25 p2.7 i/o o p2.7 : i/o port 2 b it 7. a15 : extern a l memory interf a ce addre ss b it 15. 26 32 29 26 p4.5 i/o o p4.5 : i/o port 4 b it 5. psen : extern a l memory interf a ce progr a m s tore en ab le ( a ctive-low). 27 33 30 27 p4.4 i/o o p4.4 : i/o port 4 b it 4. ale : extern a l memory interf a ce addre ss l a tch en ab le. 2 8 34 2 8 nc not intern a lly connected 29 35 31 29 pol i pol : re s et pol a rity ( s ee ?extern a l re s et? on p a ge 33. ) 30 36 32 30 p0.7 i/o i/o p0.7 : i/o port 0 b it 7. ad7 : extern a l memory interf a ce addre ss /d a t a b it 7. 31 37 33 31 p0.6 i/o i/o p0.6 : i/o port 0 b it 6. ad6 : extern a l memory interf a ce addre ss /d a t a b it 6. 32 3 8 34 32 p0.5 i/o i/o p0.5 : i/o port 0 b it 5. ad5 : extern a l memory interf a ce addre ss /d a t a b it 5. 33 39 35 33 p0.4 i/o i/o p0.4 : i/o port 0 b it 4. ad4 : extern a l memory interf a ce addre ss /d a t a b it 4. 34 40 36 34 p0.3 i/o i/o p0.3 : i/o port 0 b it 3. ad3 : extern a l memory interf a ce addre ss /d a t a b it 3. 35 41 37 35 p0.2 i/o i/o p0.2 : i/o port 0 b it 2. ad2 : extern a l memory interf a ce addre ss /d a t a b it 2. 36 42 3 8 36 p0.1 i/o i/o p0.1 : i/o port 0 b it 1. ad1 : extern a l memory interf a ce addre ss /d a t a b it 1. 37 43 39 37 p0.0 i/o i/o p0.0 : i/o port 0 b it 0. ad0 : extern a l memory interf a ce addre ss /d a t a b it 0. 3 8 44 40 3 8 vdd i su pply volt a ge 39 1 39 nc not intern a lly connected 40 2 1 40 p1.0 i/o i/o p1.0 : i/o port 1 b it 0. t2 : timer 2 extern a l inp u t or clock o u tp u t. 41 3 2 41 p1.1 i/o i p1.1 : i/o port 1 b it 1. t2ex : timer 2 extern a l c a pt u re/relo a d inp u t. 42 4 3 42 p1.2 i/o p1.2 : i/o port 1 b it 2. 43 5 4 43 p1.3 i/o p1.3 : i/o port 1 b it 3. 44 6 5 44 p1.4 i/o p1.4 : i/o port 1 b it 4. table 1-1. at 8 9lp51/52 pin de s cription pin number symbol type description tqfp plcc pdip vqfn
6 3709c?micro?5/11 at89lp51/52 - preliminary 2. overview the at 8 9lp51/52 i s a low-power, high-perform a nce cmo s 8 - b it microcontroller with 4k/ 8 k b yte s of in- s y s tem progr a mm ab le fl as h progr a m memory a nd 256 b yte s of fl as h d a t a memory. the device i s m a n u f a ct u red us ing atmel' s high-den s ity nonvol a tile memory technology a nd i s comp a ti b le with the ind us try- s t a nd a rd 8 0c52 in s tr u ction s et. the at 8 9lp51/52 i s bu ilt a ro u nd a n enh a nced cpu core th a t c a n fetch a s ingle b yte from mem- ory every clock cycle. in the cl ass ic 8 051 a rchitect u re, e a ch fetch req u ire s 6 clock cycle s , forcing in s tr u ction s to exec u te in 12, 24 or 4 8 clock cycle s . in the at 8 9lp51/52 cpu, in s tr u ction s need only 1 to 4 clock cycle s providing 6 to 12 time s more thro u ghp u t th a n the s t a nd a rd 8 051. s ev- enty percent of in s tr u ction s need only as m a ny clock cycle s as they h a ve b yte s to exec u te, a nd mo s t of the rem a ining in s tr u ction s req u ire only one a ddition a l clock. the enh a nced cpu core i s c a p ab le of 20 mip s thro u ghp u t where as the cl ass ic 8 051 cpu c a n deliver only 4 mip s a t the sa me c u rrent con su mption. conver s ely, a t the sa me thro u ghp u t as the cl ass ic 8 051, the new cpu core r u n s a t a m u ch lower s peed a nd there b y gre a tly red u cing power con su mption a nd emi. the at 8 9lp51/52 a l s o incl u de s a comp a ti b ility mode th a t will en ab le cl ass ic 12 clock per m a chine cycle oper a tion for tr u e timing comp a ti b ility with at 8 9 s 51/52. the at 8 9lp51/52 provide s the following s t a nd a rd fe a t u re s : 4k/ 8 k b yte s of in- s y s tem progr a mm ab le fl as h progr a m memory, 256 b yte s of fl as h d a t a memory, 256 b yte s of ram, u p to 36 i/o line s , three 16- b it timer/co u nter s , a progr a mm ab le w a tchdog timer, a f u ll-d u plex s eri a l port, a n on-chip cry s t a l o s cill a tor, a n intern a l 1. 8 432 mhz au xili a ry o s cill a tor, a nd a fo u r-level, s ix-vector interr u pt s y s tem. a b lock di a gr a m i s s hown in fig u re 2-1 . all three timer/co u nter s of the at 8 9lp51/52, timer 0, timer 1 a nd timer 2, c a n b e config u red to toggle a port pin on overflow for clock/w a veform gener a tion. unlike at 8 9 s 51, timer 2 i s a l s o pre s ent on at 8 9lp51. the enh a nced f u ll-d u plex uart of the at 8 9lp51/52 incl u de s fr a ming error detection a nd a u tom a tic addre ss recognition. in a ddition, enh a ncement s to mode 0 a llow h a rdw a re a cceler- a ted em u l a tion of a s eri a l peripher a l interf a ce ( s pi) or a two-wire interf a ce (twi). the w a tchdog timer of the at 8 9lp51/52 incl u de s a 7- b it pre s c a ler, a s oftw a re re s et comm a nd a nd a n overflow fl a g. the w a tchdog c a n b e config u red to o u tp u t a re s et p u l s e on the extern a l re s et pin. e a ch 8 - b it i/o port of the at 8 9lp51/52 c a n b e independently config u red in one of fo u r oper a ting mode s . in q uas i- b idirection a l mode, the port oper a te s as in the cl ass ic 8 051. in inp u t-only mode, the port i s tri s t a ted. p us h-p u ll o u tp u t mode provide s f u ll cmo s driver s a nd open-dr a in mode provide s j us t a p u ll-down. unlike other 8 051 s , thi s a llow s port 0 to oper a te with on-chip p u ll- u p s if de s ired.
7 3709c?micro?5/11 at89lp51/52 - preliminary 2.1 block diagram figure 2-1. at 8 9lp51/52 block di a gr a m 2.2 system configuration the at 8 9lp51/52 su pport s s ever a l s y s tem config u r a tion option s . nonvol a tile option s a re s et thro u gh us er f us e s th a t m us t b e progr a mmed thro u gh the fl as h progr a mming interf a ce. vol a tile option s a re controlled b y s oftw a re thro u gh individ ua l b it s of s peci a l f u nction regi s ter s ( s fr s ). the at 8 9lp51/52 m us t b e properly config u red b efore correct oper a tion c a n occ u r. 2.2.1 fuse options t ab le 2-1 li s t s the f usab le option s for the at 8 9lp51/52. the s e option s m a int a in their s t a te even when the device i s powered off, bu t c a n only b e ch a nged with a n extern a l device progr a mmer. for more inform a tion, s ee s ection 17.7 ?u s er config u r a tion f us e s ? on p a ge 8 6 . 4k/8k bytes flash code uart 16-bit timer 0 16-bit timer 1 watchdog timer configurable oscillator crystal or resonator 256 bytes flash data 16-bit timer 2 256 bytes ram xram interface 8051 single cycle cpu with 12-cycle compatibility por bod port 0 configurable i/o port 1 configurable i/o port 2 configurable i/o port 3 configurable i/o port 4 configurable i/o rc auxiliary oscillator
8 3709c?micro?5/11 at89lp51/52 - preliminary 2.2.2 software options t ab le 2-2 li s t s s ome import a nt s oftw a re config u r a tion b it s th a t a ffect oper a tion a t the s y s tem level. the s e c a n b e ch a nged b y the a pplic a tion s oftw a re bu t a re s et to their def au lt v a l u e s u pon a ny re s et. mo s t peripher a l s a l s o h a ve m u ltipe config u r a tion b it s th a t a re not li s ted here. 2.3 comparison to at89s51/52 the at 8 9lp51/52 i s p a rt of a f a mily of device s with enh a nced fe a t u re s th a t a re f u lly b in a ry com- p a ti b le with the 8 051 in s tr u ction s et. the at 8 9lp51/52 h as two mode s of oper a tion s , comp a ti b ility mode a nd f as t mode. in comp a ti b ility mode the in s tr u ction timing, peripher a l b eh a vior, s fr a ddre ss e s , b it ass ignment s a nd pin f u nction s a re identic a l to atmel' s exi s ting at 8 9 s 51/52 prod u ct. addition a l enh a ncement s a re tr a n s p a rent to the us er a nd c a n b e us ed if de s ired. f as t mode a llow s gre a ter perform a nce, bu t with s ome difference s in b eh a vior. the m a jor enh a ncement s from the at 8 9 s 51/52 a re o u tlined in the following p a r a gr a ph s a nd m a y b e us ef u l to us er s migr a ting to the at 8 9lp51/52 from older device s . a su mm a ry of the difference s b etween comp a ti b ility a nd f as t mode s i s given in t ab le 2-3 on p a ge 10 . s ee a l s o the applic a - tion note ?migr a ting from at 8 9 s 52 to at 8 9lp52.? table 2-1. u s er config u r a tion f us e s fuse name description clock s o u rce s elect s b etween the high s peed cry s t a l o s cill a tor, low s peed cry s t a l o s cill a tor, extern a l clock or intern a l rc o s cill a tor for the s o u rce of the s y s tem clock. s t a rt- u p time s elect s time-o u t del a y for the por/bod/pwd w a ke- u p period. comp a ti b ility mode config u re s the cpu in 12-clock comp a ti b ility mode or s ingle-cycle f as t mode in- s y s tem progr a mming en ab le en ab le s or di sab le s in- s y s tem progr a mming. u s er s ign a t u re progr a mming en ab le s or di sab le s progr a mming of u s er s ign a t u re a rr a y. tr i s t a te port s config u re s the def au lt port s t a te as inp u t-only mode (tri s t a ted) or q uas i- b idirection a l mode (we a kly p u lled high). in-applic a tion progr a mming en ab le s or di sab le s in-applic a tion ( s elf) progr a mming r1 en ab le table 2-2. import a nt s oftw a re config u r a tion bit s bit(s) sfr location description pxm0 pxm1 pmod config u re s the i/o mode of a ll pin s of port x to b e np u t-only, q uas i- b idirection a l, p us h-p u ll o u tp u t or open-dr a in. the def au lt s t a te i s controlled b y the def au lt port s t a te f us e ab ove cdv 2-0 clkreg.3-1 s elect s the divi s ion r a tio b etween the o s cill a tor a nd the s y s tem clock tp s 3-0 clkreg.7-4 s elect s the divi s ion r a tio b etween the s y s tem clock a nd the timer s di s ale auxr.0 en ab le s /di sab le s toggling of ale exram auxr.1 en ab le s /di sab le s a cce ss to on-chip memorie s th a t a re m a pped to the extern a l d a t a memory a ddre ss s p a ce w s 1-0 auxr.3-2 s elect s the n u m b er of w a it s t a te s when a cce ss ing extern a l d a t a memory dmen memcon.3 en ab le s /di sab le s a cce ss to the on-chip fl as h d a t a memory iap memcon.7 en b le s /di sab le s the s elf progr a mming fe a t u re when the f us e a llow s
9 3709c?micro?5/11 at89lp51/52 - preliminary 2.3.1 instruction execution in comp a ti b ility mode the at 8 9lp51/52 cpu us e s the s ix- s t a te m a chine cycle of the s t a nd a rd 8 051 where in s tr u ction b yte s a re fetched every three s y s tem clock cycle s . exec u tion time s in thi s mode a re identic a l to at 8 9 s 51/52. for gre a ter perform a nce the us er c a n en ab le f as t mode b y di sab ling the comp a ti b ility f us e. in f as t mode the cpu fetche s one code b yte from memory every clock cycle in s te a d of every three clock cycle s . thi s gre a tly incre as e s the thro u ghp u t of the cpu. e a ch s t a nd a rd in s tr u ction exec u te s in only 1 to 4 clock cycle s . s ee ?in s tr u ction s et su mm a ry? on p a ge 75 for more det a il s . any s oftw a re del a y loop s or in s tr u ction- bas ed timing oper a tion s m a y need to b e ret u ned to a chieve the de s ired re su lt s in f as t mode. 2.3.2 system clock by def au lt in comp a ti b ility mode the s y s tem clock freq u ency i s divided b y 2 from the extern a lly su pplied xtal1 freq u ency for comp a ti b ility with s t a nd a rd 8 051 s (12 clock s per m a chine cycle). the s y s tem clock divider c a n s c a le the s y s tem clock ver sus the o s cill a tor s o u rce ( s ee s ection 6.4 on p a ge 31 ). the divide- b y-2 c a n b e di sab led to oper a te in x2 mode (6 clock s per m a chine cycle) or the clock m a y b e f u rther divided to red u ce the oper a ting freq u ency. in f as t mode the clock divider def au lt s to divide b y 1. the s y s tem clock s o u rce i s s elect ab le b etween the cry s t a l o s cill a tor, a n extern a lly driven clock a nd a n intern a l 1. 8 432 mhz au xili a ry o s cill a tor. s ee ? s y s tem clock? on p a ge 29 a nd ?u s er con- fig u r a tion f us e s ? on p a ge 8 6 . 2.3.3 reset the r s t pin of the at 8 9lp51/52 h as s elect ab le pol a rity us ing the pol pin (formerly ea ). when pol i s high the r s t pin i s a ctive high with a p u ll-down re s i s tor a nd when pol i s low the r s t pin i s a ctive low with a p u ll- u p re s i s tor. for exi s ting at 8 9 s 51/52 s ocket s where ea i s tied to vdd, repl a cing at 8 9 s 51/52 with at 8 9lp51/52 will m a int a in the a ctive high re s et. note th a t forcing extern a l exec u tion b y tying ea low i s not su pported. the at 8 9lp51/52 incl u de s a n on-chip power-on re s et a nd brown-o u t detector circ u it th a t en su re s th a t the device i s re s et from s y s tem power u p. in mo s t c as e s a rc s t a rt u p circ u it i s not req u ired on the r s t pin, red u cing s y s tem co s t, a nd the r s t pin m a y b e left u nconnected if a b o a rd-level re s et i s not pre s ent. 2.3.4 timer/counters a common pre s c a ler i s a v a il ab le to divide the time bas e for timer 0, timer 1, timer 2 a nd the wdt. the tp s 3-0 b it s in the clkreg s fr control the pre s c a ler ( t ab le 6-2 on p a ge 31 ). in comp a ti b ility mode tp s 3-0 def au lt s to 0101b, which c aus e s the timer s to co u nt once every m a chine cycle. the co u nting r a te c a n b e a dj us ted line a rly from the s y s tem clock r a te to 1/16 of the s y s tem clock r a te b y ch a nging tp s 3-0 . in f as t mode tp s 3-0 def au lt s to 0000b, or the s y s tem clock r a te. tp s doe s not a ffect timer 2 in clock o u t or b au d gener a tor mode s . in comp a ti b ility mode the sa mpling of the extern a l timer/co u nter pin s : t0, t1, t2 a nd t2ex; a nd the extern a l interr u pt pin s , int0 a nd int1 , i s a l s o controlled b y the pre s c a ler. in f as t mode the s e pin s a re a lw a y s sa mpled a t the s y s tem clock r a te. both timer 0 a nd timer 1 c a n toggle their re s pective co u nter pin s , t0 a nd t1, when they over- flow b y s etting the o u tp u t en ab le b it s in tconb. the w a tchdog timer incl u de s a 7- b it pre s c a ler for longer timeo u t period s th a n the at 8 9 s 51/52. note th a t in f as t mode the wdidle a nd di s rto b it s a re loc a ted in wdtcon a nd not in auxr.
10 3709c?micro?5/11 at89lp51/52 - preliminary 2.3.5 interrupt handling with the a ddition of the iph regi s ter, the at 8 9lp51/52 provide s fo u r level s of interr u pt priority for gre a ter flexi b ility in h a ndling m u ltiple interr u pt s . al s o, f as t mode a llow s for f as ter interr u pt re s pon s e d u e to the s horter in s tr u ction exec u tion time s . 2.3.6 serial port the timer pre s c a ler incre as e s the r a nge of a chiev ab le bau d r a te s when us ing timer 1 to gener- a te the bau d r a te in uart mode s 1 or 3, incl u ding a n incre as e in the m a xim u m bau d r a te a v a il ab le in comp a ti b ility mode. addition a l fe a t u re s incl u de au tom a tic a ddre ss recognition a nd fr a ming error detection. the s hift regi s ter mode (mode 0) h as b een enh a nced with more control of the pol a rity, ph as e a nd freq u ency of the clock a nd f u ll-d u plex oper a tion. thi s a llow s em u l a tion of m as ter s eri a l pheriper a l ( s pi) a nd two-wire (twi) interf a ce s . 2.3.7 i/o ports the p0, p1, p2 a nd p3 i/o port s of the at 8 9lp51/52 m a y b e config u red in fo u r different mode s . the def au lt s etting depend s on the tri s t a te-port u s er f us e ( s ee s ection 17.7 on p a ge 8 6 ). when the f us e i s s et a ll the i/o port s revert to inp u t-only (tri s t a ted) mode a t power- u p or re s et. when the f us e i s not a ctive, port s p1, p2 a nd p3 s t a rt in q uas i- b idirection a l mode a nd p0 s t a rt s in open-dr a in mode. p4 a lw a y s oper a te s in q uas i- b idirection a l mode. p0 c a n b e config u red to h a ve intern a l p u ll- u p s b y pl a cing it in q uas i- b idirection a l or o u tp u t mode s . thi s c a n red u ce s y s - tem co s t b y removing the need for extern a l p u ll- u p s on port 0. the p4.4?p4.7 pin s a re a ddition a l i/o s th a t repl a ce the norm a lly dedic a ted ale, p s en, xtal1 a nd xtal2 pin s of the at 8 9 s 51/52. the s e pin s c a n b e us ed as a ddition a l i/o s depending on the config u r a tion of the clock a nd extern a l memory. 2.3.8 security the at 8 9lp51/52 doe s not su pport the exten a l a cce ss pin (ea ). therefore it i s not po ss i b le to exec u te from extern a l progr a m memory in a ddre ss r a nge 0000h?1fffh. when the third lock b it i s en ab led (lock mode 4) extern a l progr a m exec u tion i s di sab led for a ll a ddre ss e s ab ove 1fffh. thi s differ s from at 8 9 s 51/52 where lock mode 4 prevent s ea from b eing sa mpled low, bu t m a y s till a llow extern a l exec u tion a t a ddre ss e s o u t s ide the 8 k intern a l s p a ce. 2.3.9 programming the at 8 9lp51/52 su pport s a richer comm a nd s et for in- s y s tem progr a mming (i s p). exi s ting at 8 9 s 51/52 progr a mmer s s ho u ld b e ab le to progr a m the at 8 9lp51/52 in b yte mode. in p a ge mode the at 8 9lp51/52 only su pport s progr a mming of a h a lf-p a ge of 64 b yte s a nd therefore req u ire s a n extr a a ddre ss b yte as comp a red to at 8 9 s 51/52. f u rthermore the device s ign a t u re i s loc a ted a t a ddre ss e s 0000h, 0001h a nd 0003h in s te a d of 0000h, 0100h a nd 0200h. table 2-3. comp a ti b ility mode ver sus f as t mode su mm a ry feature compatibility fast in s tr u ction fetch in s y s tem clock s 31 in s tr u ction exec u tion time in s y s tem clock s 6, 12, 1 8 or 24 1, 2, 3, 4 or 5 def au lt s y s tem clock divi s or 2 1 def au lt timer pre s c a ler divi s or 6 1
11 3709c?micro?5/11 at89lp51/52 - preliminary 3. memory organization the at 8 9lp51/52 us e s a h a rv a rd architect u re with s ep a r a te a ddre ss s p a ce s for progr a m a nd d a t a memory. the progr a m memory h as a reg u l a r line a r a ddre ss s p a ce with su pport for 64k b yte s of directly a ddre ssab le a pplic a tion code. the d a t a memory h as 256 b yte s of intern a l ram a nd 12 8 b yte s of s peci a l f u nction regi s ter i/o s p a ce. the at 8 9lp51/52 su pport s u p to 64k b yte s of extern a l d a t a memory, with portion s of the extern a l d a t a memory s p a ce implemented on chip as nonvol a tile fl as h d a t a memory. extern a l progr a m memory i s su pported for a ddre ss e s ab ove 8 k. the memory a ddre ss s p a ce s of the at 8 9lp51/52 a re li s ted in t ab le 3-1 . 3.1 program memory the at 8 9lp51/52 cont a in s 4k/ 8 k b yte s of on-chip in- s y s tem progr a mm ab le fl as h memory for progr a m s tor a ge, pl us su pport for u p to 60k/56k b yte s of extern a l progr a m memory. the fl as h memory h as a n end u r a nce of a t le as t 10,000 write/er as e cycle s a nd a minim u m d a t a retention time of 10 ye a r s . the re s et a nd interr u pt vector s a re loc a ted within the fir s t 8 3 b yte s of progr a m memory (refer to t ab le 9-1 on p a ge 3 8 ). con s t a nt t ab le s c a n b e a lloc a ted within the entire 64k progr a m memory a ddre ss s p a ce for a cce ss b y the movc in s tr u ction. a m a p of the at 8 9lp51/52 progr a m memory i s s hown in fig u re 3-1 . pin sa mpling r a te (int0 , int1 , t0, t1, t2, t2ex) pre s c a ler r a te s y s tem clock minim u m r s t inp u t p u l s e in s y s tem clock s 12 2 wdidle a nd di s rto b it loc a tion s auxr wdtcon table 2-3. comp a ti b ility mode ver sus f as t mode su mm a ry feature compatibility fast table 3-1. at 8 9lp51/52 memory addre ss s p a ce s name description range data directly a ddre ssab le intern a l ram 00h?7fh idata indirectly a ddre ssab le intern a l ram a nd s t a ck s p a ce 00h?ffh s fr directly a ddre ssab le i/o regi s ter s p a ce 8 0h?ffh fdata on-chip nonvol a tile fl as h d a t a memory 0000h?00ffh xdata extern a l d a t a memory 0100h?ffffh code on-chip nonvol a tile fl as h progr a m memory 0000h?0fffh (at 8 9lp51) 0000h?1fffh (at 8 9lp52) xcode extern a l progr a m memory 2000h?ffffh (at 8 9lp51) 1000h?ffffh (at 8 9lp52) s ig on-chip nonvol a tile fl as h s ign a t u re a rr a y 0000h?01ffh
12 3709c?micro?5/11 at89lp51/52 - preliminary figure 3-1. progr a m memory m a p 3.1.1 external program memory interface the at 8 9lp51/52 us e s the s t a nd a rd 8 051 extern a l progr a m memory interf a ce with the u pper a ddre ss on port 2, the lower a ddre ss a nd d a t a in/o u t m u ltiplexed on port 0, a nd the ale a nd p s en s tro b e s . progr a m memory a ddre ss e s a re a lw a y s 16- b it s wide, even tho u gh the a ct ua l a mo u nt of progr a m memory us ed m a y b e le ss th a n 64k b ye s . extern a l progr a m exec u tion sa cri- fice s two f u ll 8 - b it port s , p0 a nd p2, to the f u nction of a ddre ss ing the progr a m memory. fig u re 3-2 s how s a h a rdw a re config u r a tion for a cce ss ing u p to 64k b yte s of extern a l rom us ing a 16- b it line a r a ddre ss . port 0 s erve s as a m u ltiplexed a ddre ss /d a t a bus to the rom. the addre ss l a tch en ab le s tro b e (ale) i s us ed to l a tch the lower a ddre ss b yte into a n extern a l reg- i s ter s o th a t port 0 c a n b e freed for d a t a inp u t/o u tp u t. port 2 provide s the u pper a ddre ss b yte thro u gho u t the oper a tion. p s en s tro b e s the extern a l memory. fig u re 3-3 s how s the timing of the extern a l progr a m memory interf a ce. ale i s emitted a t a con- s t a nt r a te of 1/3 of the s y s tem clock with a 1/3 d u ty cycle. p s en i s emitted a t a s imil a r r a te, bu t with 50% d u ty cycle. the new a ddre ss ch a nge s in the middle of the ale p u l s e for l a tching on the f a lling edge a nd i s tri s t a ted a t the f a lling edge of p s en . the in s tr u ction d a t a i s sa mpled from p0 a nd l a tched intern a lly d u ring the high ph as e of the clock prior to the ri s ing edge of p s en . thi s timing a pplie s to b oth comp a ti b ility a nd f as t mode s . in comp a ti b ility mode there i s no dif- ference in in s tr u ction timing b etween intern a l a nd extern a l exec u tion. figure 3-2. exec u ting from extern a l progr a m memory 0000 ffff 0000 007f user signature array 0100 01ff atmel signature array sigen=0 sigen=1 at89lp52 2000 1fff external program memory (xcode: 56kb) internal program memory (code: 8kb) 0000 ffff 0000 007f user signature array 0100 01ff atmel signature array at89lp51 1000 0fff external program memory (xcode: 60kb) internal program memory (code: 4kb) at89lp external program memory instr. addr oe psen p 3 p2 ale p0 p1 latch
13 3709c?micro?5/11 at89lp51/52 - preliminary figure 3-3. extern a l progr a m memory fetche s in order for f as t mode to fetch extern a lly, two w a it s t a te s m us t b e in s erted for every clock cycle, incre as ing the in s tr u ction exec u tion time b y a f a ctor of 3. however, d u e to other optimiz a tion s , extern a l f as t mode in s tr u ction s m a y s till b e 1/4 to 1/2 f as ter th a n their comp a ti b ility mode eq u iv- a lent s . note th a t if ale i s a llowed to toggle in f as t mode, there i s a po ss i b ility th a t when the cpu j u mp s from intern a l to extern a l exec u tion a s hort p u l s e m a y occ u r on ale as s hown in fig- u re 3-4 . the s et u p time from the a ddre ss to the f a lling edge of ale rem a in s the sa me. however, thi s b eh a vior c a n b e a voided b y s etting the di s ale b it prior to a ny j u mp ab ove the 8 k b order. figure 3-4. intern a l/extern a l progr a m memory bo u nd a ry (f as t mode) 3.1.2 sig in a ddition to the 64k code s p a ce, the at 8 9lp51/52 a l s o su pport s a 256- b yte u s er s ign a t u re arr a y a nd a 12 8 - b yte atmel s ign a t u re arr a y th a t a re a cce ss i b le b y the cpu. the atmel s ign a - t u re arr a y i s initi a lized with the device id in the f a ctory. the u s er s ign a t u re arr a y i s a v a il ab le for us er identific a tion code s or con s t a nt p a r a meter d a t a . d a t a s tored in the s ign a t u re a rr a y i s not s ec u re. s ec u rity b it s will di sab le write s to the a rr a y; however, re a d s b y a n extern a l device pro- gr a mmer a re a lw a y s a llowed. in order to re a d from the s ign a t u re a rr a y s , the s igen b it (auxr1.3) m us t b e s et ( s ee t ab le 5-3 on p a ge 2 8 ). while s igen i s one, movc a,@a+dptr will a cce ss the s ign a t u re a rr a y s . the u s er s ign a t u re arr a y i s m a pped from a ddre ss e s 0100h to 01ffh a nd the atmel s ign a t u re arr a y i s m a pped from a ddre ss e s 0000h to 007fh. s igen m us t b e cle a red b efore us ing movc to clk ale psen float pcl out p0 pch out p2 pch out pch out data sampled pcl out pcl out data sampled data sampled clk ale disale=0 psen float p0 sfr out p0 p2 sfr out p2 pch out pch out pcl out pcl out data sampled short pulse ale disale=1 internal execution external execution
14 3709c?micro?5/11 at89lp51/52 - preliminary a cce ss the code memory. the u s er s ign a t u re arr a y m a y a l s o b e modified b y the in-applic a tion progr a mming interf a ce. when iap = 1 a nd s igen = 1, movx @dptr in s tr u ction s will a cce ss the a rr a y ( s ee s ection 3.4 on p a ge 23 ). 3.2 internal data memory the at 8 9lp51/52 cont a in s 256 b yte s of gener a l s ram d a t a memory pl us 12 8 b yte s of i/o memory m a pped into a s ingle 8 - b it a ddre ss s p a ce. acce ss to the intern a l d a t a memory doe s not req u ire a ny config u r a tion. the intern a l d a t a memory h as three a ddre ss s p a ce s : data, idata a nd s fr; as s hown in fig u re 3-5 . s ome portion s of extern a l d a t a memory a re a l s o implemented intern a lly. s ee ?extern a l d a t a memory? b elow for more inform a tion. figure 3-5. intern a l d a t a memory m a p 3.2.1 data the fir s t 12 8 b yte s of ram a re directly a ddre ssab le b y a n 8 - b it a ddre ss (00h?7fh) incl u ded in the in s tr u ction. the lowe s t 32 b yte s of data memory a re gro u ped into 4 ba nk s of 8 regi s ter s e a ch. the r s 0 a nd r s 1 b it s (p s w.3 a nd p s w.4) s elect which regi s ter ba nk i s in us e. in s tr u c- tion s us ing regi s ter a ddre ss ing will only a cce ss the c u rrently s pecified ba nk. the lower 12 8 b it a ddre ss e s a re a l s o m a pped into data a ddre ss e s 20h?2fh. 3.2.2 idata the f u ll 256 b yte intern a l ram c a n b e indirectly a ddre ss ed us ing the 8 - b it pointer s r0 a nd r1. the fir s t 12 8 b yte s of idata incl u de the data s p a ce. the h a rdw a re s t a ck i s a l s o loc a ted in the idata s p a ce. 3.2.3 sfr the u pper 12 8 direct a ddre ss e s ( 8 0h?ffh) a cce ss the i/o regi s ter s . i/o regi s ter s on at 8 9lp device s a re referred to as s peci a l f u nction regi s ter s . the s fr s c a n only b e a cce ss ed thro u gh direct a ddre ss ing. all s fr loc a tion s a re not implemented. s ee s ection 4. for a li s ted of a v a il ab le s fr s . 3.3 external data memory at 8 9lp microcontroller s su pport a 16- b it extern a l memory a ddre ss s p a ce for u p to 64k b yte s of extern a l d a t a memory (xdata). the extern a l memory s p a ce i s a cce ss ed with the movx in s tr u ction s . s ome intern a l d a t a memory re s o u rce s a re m a pped into portion s of the extern a l ffh upper 128 80h 7fh lower 128 0 accessible by direct addressing ffh 80h accessible by direct and indirect addressing special function registers ports status and control bits registers stack pointer accumulator (etc.) timers accessible by indirect addressing only idata sfr data/idata
15 3709c?micro?5/11 at89lp51/52 - preliminary a ddre ss s p a ce as s hown in fig u re 3-6 . the s e memory s p a ce s m a y req u ire config u r a tion b efore the cpu c a n a cce ss them. the at 8 9lp51/52 incl u de s 256 b yte s of nonvol a tile fl as h d a t a memory (fdata). 3.3.1 xdata the extern a l d a t a memory s p a ce c a n a ccommod a te u p to 64kb of extern a l memory. the at 8 9lp51/52 us e s the s t a nd a rd 8 051 extern a l d a t a memory interf a ce with the u pper a ddre ss b yte on port 2, the lower a ddre ss b yte a nd d a t a in/o u t m u ltiplexed on port 0, a nd the ale, rd a nd wr s tro b e s . xdata c a n b e a cce ss ed with b oth 16- b it (movx @dptr) a nd 8 - b it (movx @ri) a ddre ss e s . s ee s ection 3.3.3 on p a ge 1 8 for more det a il s of the extern a l memory interf a ce. s ome intern a l d a t a memory s p a ce s a re m a pped into portion s of the xdata a ddre ss s p a ce. in thi s c as e the lower a ddre ss r a nge s will a cce ss intern a l re s o u rce s in s te a d of extern a l memory. addre ss e s ab ove the r a nge implemented intern a lly will def au lt to xdata. the at 8 9lp51/52 su pport s u p to 63.75k or 56k b yte s of extern a l memory when us ing the intern a lly m a pped mem- orie s . s etting the exram b it (auxr.1) to one will force a ll movx in s tr u ction s to a cce ss the entire 64kb xdata reg a rdle ss of their a ddre ss ( s ee ?auxr ? a u xili a ry control regi s ter? on p a ge 20 ). figure 3-6. extern a l d a t a memory m a p 3.3.2 fdata the fl as h d a t a memory i s a portion of the extern a l memory s p a ce implemented as a n intern a l nonvol a tile d a t a memory. fl as h d a t a memory i s en ab led b y s etting the dmen b it (memcon.3) to one. when iap = 0 a nd dmen = 1, the fl as h d a t a memory i s m a pped into the fdata s p a ce, a t the b ottom of the extern a l memory a ddre ss s p a ce, from 0000h to 00ffh. ( s ee fig u re 3-6 ). movx in s tr u ction s to thi s a ddre ss r a nge will a cce ss the intern a l nonvol a tile memory. fdata i s flash data (fdata: 256) 00ff 1fff 2000 flash program (code: 8kb) 0000 0100 ffff external data (xdata: 64kb) external data (xdata: 63.75kb) external data (xdata: 56kb) ffff ffff exram = 1 or dmen = 0 iap = 0 exram = 0 dmen = 1 iap = 0 exram = 0 dmen = x iap = 1
16 3709c?micro?5/11 at89lp51/52 - preliminary not a cce ss i b le while dmen = 0. fdata c a n b e a cce ss ed only b y 16- b it (movx @dptr) a ddre ss e s . movx @ri in s tr u ction s to the fdata a ddre ss r a nge will a cce ss extern a l memory. addre ss e s ab ove the fdata r a nge a re m a pped to xdata. 3.3.2.1 write protocol the fdata a ddre ss s p a ce a cce ss e s a n intern a l nonvol a tile d a t a memory. thi s a ddre ss s p a ce c a n b e re a d j us t like edata b y i ssu ing a movx a,@dptr; however, write s to fdata req u ire a more complex protocol a nd t a ke s ever a l milli s econd s to complete. for intern a l exec u tion the at 8 9lp51/52 us e s a n idle-while-write a rchitect u re where the cpu i s pl a ced in a n idle s t a te while the write occ u r s . when the write complete s , the cpu will contin u e exec u ting with the in s tr u ction a fter the movx @dptr,a in s tr u ction th a t s t a rted the write. all peripher a l s will contin u e to f u nction d u ring the write cycle; however, interr u pt s will not b e s er- viced u ntil the writ e complete s . for extern a l exec u tion the at 8 9lp51/52 us e s a n execute-while-write a rchitect u re where the cpu contin u e s to oper a te while the write occ u r s . the s oftw a re s ho u ld poll the s t a te of the bu s y fl a g to determine when the write complete s . interr u pt s m us t b e di sab led d u ring the write s eq u ence as the cpu will not b e ab le to vector to the intern a l interr u pt t ab le a nd c a re s ho u ld b e t a ken th a t the a pplic a tion doe s not j u mp to a n intern a l a ddre ss u ntil the writ e complete s . to en ab le write a cce ss to the nonvol a tile d a t a memory, the mwen b it (memcon.4) m us t b e s et to one. when mwen = 1 a nd dmen = 1, movx @dptr,a m a y b e us ed to write to fdata. fdata us e s fl as h memory with a p a ge- bas ed progr a mming model. fl as h d a t a memory differ s from tr a dition a l eeprom d a t a memory in the method of writing d a t a . eeprom gener a lly c a n u pd a te a s ingle b yte with a ny v a l u e. fl as h memory s plit s progr a mming into write a nd er as e oper a tion s . a fl as h write c a n only progr a m zeroe s , i.e ch a nge one s into zeroe s (). any one s in the write d a t a a re ignored. a fl as h er as e s et s a n entire p a ge of d a t a to one s s o th a t a ll b yte s b ecome ffh. therefore a fter a n er as e, e a ch b yte in the p a ge c a n only b e written once with a ny po ss i b le v a l u e. byte s c a n b e overwritten witho u t a n er as e as long as only one s a re ch a nged into zeroe s . however, if even a s ingle b it need s u pd a ting from zero to one ( ); then the content s of the p a ge m us t fir s t b e sa ved, the entire p a ge m us t b e er as ed a nd the zero b it s in a ll b yte s (old a nd new d a t a com b ined) m us t b e written. avoiding u nnece ssa ry p a ge er as e s gre a tly improve s the end u r a nce of the memory.. the at 8 9lp51/52 incl u de s 2 d a t a p a ge s of 12 8 b yte s e a ch. one or more b yte s in a p a ge m a y b e written a t one time. the at 8 9lp51/52 incl u de s a tempor a ry p a ge bu ffer of 64 b yte s , or h a lf of a p a ge. bec aus e the p a ge bu ffer i s 64 b yte s long, the m a xim u m n u m b er of b yte s written a t one time i s 64. therefore, two write cycle s a re req u ired to fill the entire 12 8 - b yte p a ge, one for the low h a lf p a ge (00h?3fh) a nd one for the high h a lf p a ge (40h?7fh) as s hown in fig u re 3-7 . figure 3-7. p a ge progr a mming s tr u ct u re 10 3 f data memory high half page 40 7f 00 3 f page buffer
17 3709c?micro?5/11 at89lp51/52 - preliminary the ldpg b it (memcon.5) a llow s m u ltiple d a t a b yte s to b e lo a ded to the tempor a ry p a ge bu f- fer. while ldpg = 1, movx @dptr,a in s tr u ction s will lo a d d a t a to the p a ge bu ffer, bu t will not s t a rt a write s eq u ence. note th a t a previo us ly lo a ded b yte m us t not b e relo a ded prior to the write s eq u ence. to write the h a lf p a ge into the memory, ldpg m us t fir s t b e cle a red a nd then a movx @dptr,a with the fin a l d a t a b yte i s i ssu ed. the a ddre ss of the fin a l movx determine s which h a lf p a ge will b e written. if a movx @dptr,a in s tr u ction i s i ssu ed while ldpg = 0 with- o u t lo a ding a ny previo us b yte s , only a s ingle b yte will b e written. the p a ge bu ffer i s re s et a fter e a ch write oper a tion. fig u re s 3- 8 a nd fig u re 3-9 on p a ge 17 s how the difference b etween b yte write s a nd p a ge write s . figure 3-8. fdata byte write figure 3-9. fdata p a ge write the au to-er as e b it aer s (memcon.6) c a n b e s et to one to perform a p a ge er as e au tom a tic a lly a t the b eginning of a ny write s eq u ence. the p a ge er as e will er as e the entire p a ge, i.e. b oth the low a nd high h a lf p a ge s . however, the write oper a tion p a ired with the au to-er as e c a n only pro- gr a m one of the h a lf p a ge s . a s econd write cycle witho u t au to-er as e i s req u ired to u pd a te the other h a lf p a ge. freq u ently j us t a few b yte s within a p a ge m us t b e u pd a ted while m a int a ining the s t a te of the other b yte s . there a re two option s for h a ndling thi s s it ua tion th a t a llow the fl as h d a t a memory to em u l a te a tr a dition a l eeprom memory. the s imple s t method i s to copy the entire p a ge into a bu ffer a lloc a ted in ram, modify the de s ired b yte loc a tion s in the ram bu ffer, a nd then lo a d a nd write ba ck fir s t the low h a lf p a ge (with au to-er as e) a nd then the high h a lf p a ge to the fl as h mem- ory. thi s option req u ire s th a t a t le as t one p a ge s ize of ram i s a v a il ab le as a tempor a ry bu ffer. the s econd option i s to s tore only one h a lf p a ge in ram. the u nmodified b yte s of the other p a ge a re lo a ded directly into the fl as h memory? s tempor a ry lo a d bu ffer b efore lo a ding the u pd a ted v a l u e s of the modified b yte s . for ex a mple, if j us t the low h a lf p a ge need s modific a tion, the us er m us t fir s t s tore the high h a lf p a ge to ram, followed b y re a ding a nd lo a ding the u n a ffected b yte s of the low h a lf p a ge into the p a ge bu ffer. then the modified b yte s of the low h a lf p a ge a re s tored mwen dmen t wc ldpg idle movx t wc mwen dmen t wc ldpg idle movx
18 3709c?micro?5/11 at89lp51/52 - preliminary to the p a ge bu ffer b efore s t a rting the au to-er as e s eq u ence. the s tored v a l u e of the high h a lf p a ge m us t b e written witho u t au to-er as e a fter the progr a mming of the low h a lf p a ge complete s . thi s method red u ce s the a mo u nt of ram req u ired; however, more s oftw a re overhe a d i s needed b ec aus e the re a d- a nd-lo a d- ba ck ro u tine m us t s kip tho s e b yte s in the p a ge th a t need to b e u pd a ted in order to prevent tho s e loc a tion s in the bu ffer from b eing lo a ded with the previo us d a t a , as thi s will b lock the new d a t a from b eing lo a ded correctly. a write s eq u ence will not occ u r if the brown-o u t detector i s a ctive. if a write c u rrently in progre ss i s interr u pted b y the bod d u e to a low volt a ge condition, the err fl a g will b e s et. 3.3.3 external data memory interface the at 8 9lp51/52 us e s the s t a nd a rd 8 051 extern a l d a t a memory interf a ce with the u pper a ddre ss on port 2, the lower a ddre ss a nd d a t a in/o u t m u ltiplexed on port 0, a nd the ale, rd a nd wr s tro b e s . the interf a ce m a y b e us ed in two different config u r a tion s depending on which type of movx in s tr u ction i s us ed to a cce ss xdata. fig u re 3-10 s how s a h a rdw a re config u r a tion for a cce ss ing u p to 64k b yte s of extern a l ram us ing a 16- b it line a r a ddre ss . port 0 s erve s as a m u ltiplexed a ddre ss /d a t a bus to the ram. the addre ss l a tch en ab le s tro b e (ale) i s us ed to l a tch the lower a ddre ss b yte into a n extern a l reg- i s ter s o th a t port 0 c a n b e freed for d a t a inp u t/o u tp u t. port 2 provide s the u pper a ddre ss b yte thro u gho u t the oper a tion. the movx @dptr in s tr u ction s us e line a r addre ss mode. table 3-2. memcon ? memory control regi s ter memcon = 96h re s et v a l u e = 0000 0xxxb not bit addre ssab le iap aer s ldpg mwen dmen err bu s y wrtinh bit76543210 symbol function iap in-applic a tion progr a mming en ab le. when iap = 1 a nd the iap f us e i s en ab led, progr a mming of the code/ s ig s p a ce i s en ab led a nd movx @dptr in s tr u ction s will a cce ss code/ s ig in s te a d of edata or fdata. cle a r iap to di sab le progr a mming of code/ s ig a nd a llow a cce ss to edata a nd fdata. aer s a u to-er as e en ab le. s et to perform a n au to-er as e of a fl as h memory p a ge (code, s ig or fdata) d u ring the next write s eq u ence. cle a r to perform write witho u t er as e. ldpg lo a d p a ge en ab le. s et to thi s b it to lo a d m u ltiple b yte s to the tempor a ry p a ge bu ffer. byte loc a tion s m a y not b e lo a ded more th a n once b efore a write. ldpg m us t b e cle a red b efore writing. mwen memory write en ab le. s et to en ab le progr a mming of a nonvol a tile memory loc a tion (code, s ig or fdata). cle a r to di sab le progr a mming of a ll nonvol a tile memorie s . dmen d a t a memory en ab le. s et to en ab le nonvol a tile d a t a memory a nd m a p it into the fdata s p a ce. cle a r to di sab le nonvol a tile d a t a memory. err error fl a g. s et b y h a rdw a re if a n error occ u rred d u ring the l as t progr a mming s eq u ence d u e to a b rowno u t condition (low volt a ge on vdd). m us t b e cle a red b y s oftw a re. bu s y b us y fl a g. wrtinh write inhi b it fl a g. cle a red b y h a rdw a re when the volt a ge on vdd h as f a llen b elow the minim u m progr a mming volt a ge. s et b y h a rdw a re when the volt a ge on vdd i s ab ove the minim u m progr a mming volt a ge.
19 3709c?micro?5/11 at89lp51/52 - preliminary figure 3-10. extern a l d a t a memory 16- b it line a r addre ss mode fig u re 3-11 s how s a h a rdw a re config u r a tion for a cce ss ing 256- b yte b lock s of extern a l ram us ing a n 8 - b it p a ged a ddre ss . port 0 s erve s as a m u ltiplexed a ddre ss /d a t a bus to the ram. the ale s tro b e i s us ed to l a tch the a ddre ss b yte into a n extern a l regi s ter s o th a t port 0 c a n b e freed for d a t a inp u t/o u tp u t. the port 2 i/o line s (or other port s ) c a n provide control line s to p a ge the memory; however, thi s oper a tion i s not h a ndled au tom a tic a lly b y h a rdw a re. the s oftw a re a ppli- c a tion m us t ch a nge the port 2 regi s ter when a ppropri a te to a cce ss different p a ge s . the movx @ri in s tr u ction s us e p a ged addre ss mode. figure 3-11. extern a l d a t a memory 8 - b it p a ged addre ss mode note th a t prior to us ing the extern a l memory interf a ce, wr (p3.6) a nd rd (p3.7) m us t b e config- u red as o u tp u t s . s ee s ection 10.1 ?port config u r a tion? on p a ge 41 . p0 a nd p2 a re config u red au tom a tic a lly to p us h-p u ll o u tp u t mode when o u tp u tting a ddre ss or d a t a a nd p0 i s au tom a tic a lly tri s t a ted when inp u tting d a t a reg a rdle ss of the port config u r a tion. the port 0 config u r a tion will determine the idle s t a te of port 0 when not a cce ss ing the extern a l memory. fig u re 3-12 a nd fig u re 3-13 s how ex a mple s of extern a l d a t a memory write a nd re a d cycle s , re s pectively. the a ddre ss on p0 a nd p2 i s s t ab le a t the f a lling edge of ale. the idle s t a te of ale i s controlled b y di s ale (auxr.0). when di s ale = 0 the ale toggle s a t a con s t a nt r a te when not a cce ss ing extern a l memory. when di s ale = 1 the ale i s we a kly p u lled high. di s ale m us t b e one in order to us e p4.4 as a gener a l-p u rpo s e i/o. the w s b it s in auxr c a n extended the rd a nd wr s tro b e s b y 1, 2 or 3 cycle s as s hown in fig u re s 3-16, 3-17 a nd 3-1 8 . if a longer s tro b e i s req u ired, the a pplic a tion c a n s c a le the s y s tem clock with the clock divider to meet the req u irement s ( s ee s ection 6.4 on p a ge 31 ). p1 p0 ale p2 rd p 3 wr at89lp data latch external data memory we addr oe p1 p0 i/o ale p2 rd p 3 wr at89lp data latch external data memory we addr pag e bits oe
20 3709c?micro?5/11 at89lp51/52 - preliminary note s : 1. auxr.4 a nd auxr.3 f u nction as wdidle a nd di s rto only in comp a ti b ility mode. in f as t mode the s e b it s a re loc a ted in wdtcon. 2. w s 1 i s only a v a il ab le in f as t mode. w s 1 i s forced to 0 in comp a ti b ility mode. figure 3-12. f as t mode extern a l d a t a memory write cycle (w s =00b) table 3-3. auxr ? a u xili a ry control regi s ter auxr = 8 eh re s et v a l u e = xxx0 0000b not bit addre ssab le ???wdidle (1) di s rto (1) w s 1 (2) w s 0 exram di s ale bit76543210 symbol function wdidle wdt di sab le d u ring idle (1) . when wdidle = 0 the wdt contin u e s to co u nt in idle mode. when wdidle = 1 the wdt h a lt s co u nting in idle mode. di s rto di sab le re s et o u tp u t (1) . when di s tro = 0 the re s et pin i s driven to the sa me level as pol when the wdt re s et s . when di s rto = 1 the re s et pin i s inp u t only. w s [1-0] w a it s t a te s elect. determine s the n u m b er of w a it s t a te s in s erted into extern a l memory a cce ss e s . w s 1 (2) w s 0 w a it s t a te s rd / wr s tro b e width ale to rd / wr s et u p 000 1 x t cyc (f as t); 3 x t cyc (comp a ti b ility) 1 x t cyc (f as t); 1.5 x t cyc (comp a ti b ility) 011 2 x t cyc (f as t); 15 x t cyc (comp a ti b ility) 1 x t cyc (f as t); 1.5 x t cyc (comp a ti b ility) 102 2 x t cyc (f as t) 2 x t cyc (f as t) 113 3 x t cyc (f as t) 2 x t cyc (f as t) exram extern a l ram en ab le. when exram = 0, movx in s tr u ction s c a n a cce ss the intern a lly m a pped portion s of the a ddre ss s p a ce. acce ss e s to a ddre ss e s ab ove intern a lly m a pped memory will a cce ss extern a l memory. s et exram = 1 to b yp ass the intern a l memory a nd m a p the entire a ddre ss s p a ce to extern a l memory. di s ale ale di sab le. when di s ale = 0 the ale p u l s e i s a ctive a t 1/3 of the s y s tem clock freq u ency in comp a ti b ility mode a nd 1/2 of the s y s tem clock freq u ency in f as t mode. when di s ale s = 1 the ale i s in a ctive (high) u nle ss a n extern a l memory a cce ss occ u r s . di s ale m us t b e s et to us e p4.4 as a gener a l i/o. s1 s2 s 3 s4 clk ale wr dpl or ri out p0 sfr p0 sfr p0 p2 sfr p2 sfr dph or p2 out p2 data out
21 3709c?micro?5/11 at89lp51/52 - preliminary figure 3-13. f as t mode extern a l d a t a memory re a d cycle (w s =00b) figure 3-14. comp a ti b ility mode extern a l d a t a memory write cycle (w s 0=0) figure 3-15. comp a ti b ility mode extern a l d a t a memory re a d cycle (w s 0=0) s1 s2 s 3 s4 clk ale rd float data sampled dpl or ri out p0 sfr p0 sfr p0 p2 sfr p2 sfr dph or p2 out p2 s4 s5 s6 s1 clk ale wr dpl or ri out p0 sfr pcl or p0 sfr p0 pch or p2 sfr pch or p2 sfr dph or p2 out p2 data out s2 s 3 s4 s5 clk ale rd float data sampled dpl or ri out p0 sfr pcl or p0 sfr p0 pch or p2 sfr pch or p2 sfr dph or p2 out p2 s4 s5 s6 s1 s2 s 3 s4 s5
22 3709c?micro?5/11 at89lp51/52 - preliminary figure 3-16. movx with one w a it s t a te (w s =01b) figure 3-17. movx with two w a it s t a te s (w s =10b) figure 3-18. movx with three w a it s t a te s (w s =11b) s1 s2 s 3 w1 clk ale wr dpl out p0 sfr p0 sfr p0 p2 sfr p2 sfr dph or p2 out p2 data out s4 rd dpl out p0 sfr p0 sfr p0 float s1 s2 s 3 w1 clk ale wr dpl out p0 sfr p0 sfr p0 p2 sfr p2 sfr dph or p2 out p2 data out w2 rd dpl out p0 sfr p0 sfr p0 float s4 s1 s2 s 3 w1 clk ale wr dpl out p0 sfr p0 sfr p0 p2 sfr p2 sfr dph or p2 out p2 data out w2 rd dpl out p0 sfr p0 sfr p0 float w 3 s4
23 3709c?micro?5/11 at89lp51/52 - preliminary 3.4 in-application programming (iap) the at 8 9lp51/52 su pport s in-applic a tion progr a mming (iap), a llowing the progr a m memory to b e modified d u ring exec u tion. iap c a n b e us ed to modify the us er a pplic a tion on the fly or to us e progr a m memory for nonvol a tile d a t a s tor a ge. the sa me p a ge s tr u ct u re write protocol for fdata a l s o a pplie s to iap ( s ee s ection 3.3.2.1 ?write protocol? on p a ge 16 ). the cpu i s a lw a y s pl a ced in idle while modifying the progr a m memory. when the write complete s , the cpu will contin u e exec u ting with the in s tr u ction a fter the movx @dptr,a in s tr u ction th a t s t a rted the write. to en ab le a cce ss to the progr a m memory, the iap b it (memcon.7) m us t b e s et to one a nd the iap u s er f us e m us t b e en ab led. the iap u s er f us e c a n di sab le a ll iap oper a tion s . when thi s f us e i s di sab led, the iap b it will b e forced to 0. while iap i s en ab led, a ll movx @dptr in s tr u c- tion s will a cce ss the code s p a ce in s te a d of edata/fdata/xdata. iap a l s o a llow s reprogr a mming of the u s er s ign a t u re arr a y when s igen = 1. the iap a cce ss s etting s a re su m- m a rized in t ab le 3-4 a nd t ab le 3-5 . note: when in-applic a tion progr a mming i s not req u ired, it i s recommended th a t the iap u s er f us e b e di sab led. table 3-4. iap acce ss s etting s for at 8 9lp52 iap sigen dmen movx @dptr movc @dptr 0 0 0 xdata (0000?ffffh) code (0000?1fffh) xcode (2000?ffffh) 001 fdata (0000?00ffh) xdata (0100?ffffh) code (0000?1fffh) xcode (2000?ffffh) 0 1 0 xdata (0000?ffffh) s ig (0000?01ffh) 011 fdata (0000?00ffh) xdata (0100?ffffh) s ig (0000?01ffh) 10x code (0000?1fffh) xdata (2000?ffffh) code (0000?1fffh) xcode (2000?ffffh) 11x s ig (0000?01ffh) xdata (2000?ffffh) s ig (0000?01ffh) table 3-5. iap acce ss s etting s for at 8 9lp51 iap sigen dmen movx @dptr movc @dptr 0 0 0 xdata (0000?ffffh) code (0000?0fffh) xcode (1000?ffffh) 001 fdata (0000?00ffh) xdata (0100?ffffh) code (0000?0fffh) xcode (1000?ffffh) 0 1 0 xdata (0000?ffffh) s ig (0000?01ffh) 011 fdata (0000?00ffh) xdata (0100?ffffh) s ig (0000?01ffh) 10x code (0000?0fffh) xdata (1000?ffffh) code (0000?0fffh) xcode (1000?ffffh) 11x s ig (0000?01ffh) xdata (1000?ffffh) s ig (0000?01ffh)
24 3709c?micro?5/11 at89lp51/52 - preliminary 4. special function registers a m a p of the on-chip memory a re a c a lled the s peci a l f u nction regi s ter ( s fr) s p a ce i s s hown in t ab le 4-1 . note th a t not a ll of the a ddre ss e s a re occ u pied, a nd u nocc u pied a ddre ss e s m a y not b e imple- mented on the chip. re a d a cce ss e s to the s e a ddre ss e s will in gener a l ret u rn r a ndom d a t a , a nd write a cce ss e s will h a ve a n indetermin a te effect. u s er s oftw a re s ho u ld not write to the s e u nli s ted loc a tion s , s ince they m a y b e us ed in f u t u re prod u ct s to invoke new fe a t u re s . note s :1.all s fr s in the left-mo s t col u mn a re b it- a ddre ssab le. 2. re s et v a l u e i s 0101 0101b when tri s t a te-port f us e i s en ab led a nd 0000 0011b when di sab led. 3. re s et v a l u e i s 0101 0010b when comp a ti b ility mode i s en ab led a nd 0000 0000b when di sab led. table 4-1. at 8 9lp51/52 s fr m a p a nd re s et v a l u e s 8 9abcdef 0f 8 h 0ffh 0f0h b 0000 0000 0f7h 0e 8 h 0efh 0e0h acc 0000 0000 0e7h 0d 8 h 0dfh 0d0h p s w 0000 0000 0d7h 0c 8 ht2con 0000 0000 t2mod 0000 0000 rcap2l 0000 000 rcap2h 0000 0000 tl2 0000 000 th2 0000 0000 0cfh 0c0h p4 1111 1111 pmod (2) 0c7h 0b 8 h ip xx00 0000 s aden 0000 0000 0bfh 0b0h p3 1111 1111 iph xx00 0000 0b7h 0a 8 h ie 0x00 0000 s addr 0000 0000 0afh 0a0h p2 1111 1111 auxr1 0000 00x0 wdtr s t (write-only) wdtcon 0000 0xx0 0a7h 9 8 h s con 0000 0000 s buf xxxx xxxx 9fh 90h p1 1111 1111 tconb 000x xxxx memcon 0000 00xx 97h 88 h tcon 0000 0000 tmod 0000 0000 tl0 0000 0000 tl1 0000 0000 th0 0000 0000 th1 0000 0000 auxr 0000 0000 clkreg (3) 8 fh 8 0h p0 1111 1111 s p 0000 0111 dp0l 0000 0000 dp0h 0000 0000 dp1l 0000 0000 dp1h 0000 0000 pcon 000x 0000 8 7h 01234567
25 3709c?micro?5/11 at89lp51/52 - preliminary 5. enhanced cpu the at 8 9lp51/52 us e s a n enh a nced 8 051 cpu th a t r u n s a t 6 to 12 time s the s peed of s t a nd a rd 8 051 device s (or 3 to 6 time s the s peed of x2 8 051 device s ). the incre as e in perform a nce i s d u e to two f a ctor s . fir s t, the cpu fetche s one in s tr u ction b yte from the code memory every clock cycle. s econd, the cpu us e s a s imple two- s t a ge pipeline to fetch a nd exec u te in s tr u ction s in p a r a llel. thi s bas ic pipelining concept a llow s the cpu to o b t a in u p to 1 mip s per mhz. the at 8 9lp51/52 a l s o h as a comp a ti b ility mode th a t pre s erve s the 12-clock m a chine cycle of s t a n- d a rd 8 051 s like the at 8 9 s 51/52. 5.1 fast mode f as t ( s ingle-cycle) mode m us t b e en ab led b y cle a ring the comp a ti b ility u s er f us e. ( s ee ?u s er config u r a tion f us e s ? on p a ge 8 6 .) in thi s mode one in s tr u ction b yte i s fetched every s y s tem clock cycle. the 8 051 in s tr u ction s et a llow s for in s tr u ction s of v a ri ab le length from 1 to 3 b yte s . in a s ingle-clock-per- b yte-fetch s y s tem thi s me a n s e a ch in s tr u ction t a ke s a t le as t as m a ny clock s as it h as b yte s to exec u te. the m a jority of in s tr u ction s in the at 8 9lp51/52 follow thi s r u le: the in s tr u ction exec u tion time in s y s tem clock cycle s eq ua l s the n u m b er of b yte s per in s tr u ction, with a few exception s . br a nche s a nd c a ll s req u ire a n a ddition a l cycle to comp u te the t a rget a ddre ss a nd s ome other complex in s tr u ction s req u ire m u ltiple cycle s . s ee ?in s tr u ction s et su mm a ry? on p a ge 75. for more det a iled inform a tion on individ ua l in s tr u ction s . ex a mple of f as t mode in s tr u ction s a re s hown in fig u re 5-1 . note th a t f as t mode in s tr u ction s t a ke three time s as long to exec u te if they a re fetched from extern a l progr a m memory. figure 5-1. in s tr u ction exec u tion s eq u ence s in f as t mode read next opcode (a) 1-byte, 1-cycle instruction, e.g. inc a s1 (b) 2-byte, 2-cycle instruction, e.g. add a, #data s1 s2 read next opcode read operand (c) 1-byte, 2-cycle instruction, e.g. inc dptr s1 s2 read next opcode (d) movx (1-byte, 4-cycle) s1 s2 s 3 s4 addr data access external memory clk read next opcode
26 3709c?micro?5/11 at89lp51/52 - preliminary 5.2 compatibility mode comp a ti b ility (12-clock) mode i s en ab led b y def au lt from the f a ctory or b y s etting the comp a ti- b ility u s er f us e. in comp a ti b ility mode in s tr u ction b yte s a re fetched every three s y s tem clock cycle s a nd the cpu oper a te s with 6- s t a te m a chine cycle s a nd a divide- b y-2 s y s tem clock for 12 o s cill a tor period s per m a chine cycle. s t a nd a rd in s tr u ction s exec u te in1, 2 or 4 m a chine cycle s . in s tr u ction timing in thi s mode i s comp a ti b le with s t a nd a rd 8 051 s su ch as the at 8 9 s 51/52. comp a ti b ility mode c a n b e us ed to pre s erve the exec u tion profile s of leg a cy a pplic a tion s . for a su mm a ry of difference s b etween f as t a nd comp a ti b ility mode s s ee t ab le 2-3 on p a ge 10 . ex a mple s of comp a ti b ility mode in s tr u ction s a re s hown in fig u re 5-2 . figure 5-2. in s tr u ction exec u tion s eq u ence s in comp a ti b ility mode 5.3 enhanced dual data pointers the at 8 9lp51/52 provide s two 16- b it d a t a pointer s : dptr0 formed b y the regi s ter p a ir dpol a nd dpoh ( 8 2h a n 8 3h), a nd dptr1 formed b y the regi s ter p a ir dp1l a nd dp1h ( 8 4h a nd 8 5h). the d a t a pointer s a re us ed b y s ever a l in s tr u ction s to a cce ss the progr a m or d a t a memo- rie s . the d a t a pointer config u r a tion regi s ter (auxr1) control s oper a tion of the d ua l d a t a pointer s ( t ab le 5-3 on p a ge 2 8 ). the dp s b it in auxr1 s elect s which d a t a pointer i s c u rrently referenced b y in s tr u ction s incl u ding the dptr oper a nd. e a ch d a t a pointer m a y b e a cce ss ed a t it s re s pective s fr a ddre ss e s reg a rdle ss of the dp s v a l u e. the at 8 9lp51/52 provide s two method s for f as t context s witching of the d a t a pointer s : s1 s 1 s2 s 2 s 3 s 3 s4 s 4 s5 s 5 s6 s 6 s1 s 1 s2 s 2 s 3 s 3 s4 s 4 s5 s 5 s6 s 6 s1 s 1 s2 s 2 s 3 s 3 s4 s 4 s5 s 5 s6 s 6 s1 s 1 s2 s 2 s 3 s 3 s4 s 4 s5 s 5 s6 s 6 s1 s 1 s2 s 2 s 3 s 3 s4 s 4 s5 s 5 s6 s 6 s1 s 1 s2 s 2 s 3 s 3 s4 s 4 s5 s 5 s6 s 6 s1 s 1 s2 s 2 s 3 s 3 s4 s 4 s5 s 5 s6 s 6 s1 s 1 s2 s 2 s 3 s 3 s4 s 4 s5 s 5 s6 s 6 s1 s 1 clk c l k ale a l e read opcode r e a d o p c o d e (a) 1-byte, 1-cycle instruction, e.g., inc a a (b) 2-byte, 1-cycle instruction, e.g., add a, #data ( b ) 2 - b y t e , 1 - c y c l e i n s t r u c t i o n , e . g . , a d d a , # d a t a (c) 1-byte, 2-cycle instruction, e.g., inc dptr ( c ) 1 - b y t e , 2 - c y c l e i n s t r u c t i o n , e . g . , i n c d p t r (d) movx (1-byte, 2-cycle) ( d ) m o v x ( 1 - b y t e , 2 - c y c l e ) read next r e a d n e x t opcode o p c o d e (discard) ( d i s c a r d ) read next opcode again r e a d n e x t o p c o d e a g a i n read opcode r e a d o p c o d e read 2nd r e a d 2 n d byte b y t e read next opcode r e a d n e x t o p c o d e read opcode r e a d o p c o d e read next r e a d n e x t opcode again o p c o d e a g a i n read r e a d opcode o p c o d e (movx) ( m o v x ) no n o ale a l e read next r e a d n e x t opcode (discard) o p c o d e ( d i s c a r d ) read next r e a d n e x t opcode o p c o d e again a g a i n no n o fetch f e t c h da d a t a access external memor a c c e s s e x t e r n a l m e m o r y addr a d d r no n o fetch f e t c h read next r e a d n e x t opcode (discard) o p c o d e ( d i s c a r d )
27 3709c?micro?5/11 at89lp51/52 - preliminary ? bit 2 of auxr1 i s h a rd-wired as a logic 0. the dp s b it m a y b e toggled (to s witch d a t a pointer s ) s imply b y incrementing the auxr1 regi s ter, witho u t a ltering other b it s in the regi s ter u nintention a lly. thi s i s the preferred method when only a s ingle d a t a pointer will b e us ed a t one time. ex: inc auxr1 ; toggle dps ?in s ome c as e s , b oth d a t a pointer s m us t b e us ed s im u lt a neo us ly. to prevent freq u ent toggling of dp s , the at 8 9lp51/52 su pport s a prefix not a tion for s electing the oppo s ite d a t a pointer per in s tr u ction. all dptr in s tr u ction s , with the exception of jmp @a+dptr, when prefixed with a n 0a5h opcode will us e the inver s e v a l u e of dp s (dp s ) to s elect the d a t a pointer. s ome ass em b ler s m a y su pport thi s oper a tion b y us ing the /dptr oper a nd. for ex a mple, the following code perform s a b lock copy within edata: mov auxr1, #00h ; dps = 0 mov dptr, #src ; load source address to dptr0 mov /dptr, #dst ; load destination address to dptr1 mov r7, #blksize ; number of bytes to copy copy: movx a, @dptr ; read source (dptr0) inc dptr ; next src (dptr0+1) movx @/dptr, a ; write destination (dptr1) inc /dptr ; next dst (dptr1+1) djnz r7, copy for ass em b ler s th a t do not su pport thi s not a tion, the 0a5h prefix m us t b e decl a red in-line: ex: db 0a5h inc dptr ; equivalent to inc /dptr a su mm a ry of d a t a pointer in s tr u ction s with f as t context s witching i s li s ted in t ab le 5-1 . 5.3.1 data pointer update the d ua l d a t a pointer s on the at 8 9lp51/52 incl u de two fe a t u re s th a t control how the d a t a pointer s a re u pd a ted. the d a t a pointer decrement b it s , dpd1 a nd dpd0 in auxr1, config u re the inc dptr in s tr u ction to a ct as dec dptr. the re su lting oper a tion will depend on dp s as s hown in t ab le 5-2 . the s e b it s a l s o control the direction of au to- u pd a te s d u ring movc a nd movx. table 5-1. d a t a pointer in s tr u ction s instruction operation dps = 0 dps = 1 jmp @a+dptr jmp @a+dptr0 jmp @a+dptr1 mov dptr, #d a t a 16 mov dptr0, #d a t a 16 mov dptr1, #d a t a 16 mov /dptr, #d a t a 16 mov dptr1, #d a t a 16 mov dptr0, #d a t a 16 inc dptr inc dptr0 inc dptr1 inc /dptr inc dptr1 inc dptr0 movc a,@a+dptr movc a,@a+dptr0 movc a,@a+dptr1 movc a,@a+/dptr movc a,@a+dptr1 movc a,@a+dptr0 movx a,@dptr movx a,@dptr0 movx a,@dptr1 movx a,@/dptr movx a,@dptr1 movx a,@dptr0 movx @dptr, a movx @dptr0, a movx @dptr1, a movx @/dptr, a movx @dptr1, a movx @dptr0, a
28 3709c?micro?5/11 at89lp51/52 - preliminary the d a t a pointer u pd a te b it s , dpu1 a nd dpu0, a llow movx @dptr a nd movc @dptr in s tr u ction s to u pd a te the s elected d a t a pointer au tom a tic a lly in a po s t-increment or po s t-decre- ment f as hion. the direction of u pd a te depend s on the dpd1 a nd dpd0 b it s as s hown in t ab le 5-4 . the s e b it s c a n b e us ed to m a ke b lock copy ro u tine s more efficient. table 5-2. d a t a pointer decrement beh a vior dpd1 dpd0 equivalent operation for inc dptr and inc /dptr dps = 0 dps = 1 inc dptr inc /dptr inc dptr inc /dptr 0 0 inc dptr0 inc dptr1 inc dptr1 inc dptr0 0 1 dec dptr0 inc dptr1 inc dptr1 dec dptr0 1 0 inc dptr0 dec dptr1 dec dptr1 inc dptr0 1 1 dec dptr0 dec dptr1 dec dptr1 dec dptr0 table 5-3. auxr1 ? d a t a pointer config u r a tion regi s ter auxr1 = a2h re s et v a l u e = 0000 00x0b not bit addre ssab le dpu1 dpu0 dpd1 dpd0 s igen 0 ? dp s bit76543210 symbol function dpu1 d a t a pointer 1 upd a te. when s et, movx @dptr a nd movc @dptr in s tr u ction s th a t us e dptr1 will a l s o u pd a te dptr1 bas ed on dpd1. if dpd1 = 0 the oper a tion i s po s t-increment a nd if dpd1 = 1 the oper a tion i s po s t-decrement. when dpu1 = 0, dptr1 i s not u pd a ted. dpu0 d a t a pointer 0 upd a te. when s et, movx @dptr a nd movc @dptr in s tr u ction s th a t us e dptr0 will a l s o u pd a te dptr0 bas ed on dpd0. if dpd0 = 0 the oper a tion i s po s t-increment a nd if dpd0 = 1 the oper a tion i s po s t-decrement. when dpu0 = 0, dptr0 i s not u pd a ted. dpd1 d a t a pointer 1 decrement. when s et, inc dptr in s tr u ction s t a rgeted to dptr1 will decrement dptr1. when cle a red, inc dptr in s tr u ction s will increment dptr1. dpd1 a l s o determine s the direction of au to- u pd a te for dptr1 when dpu1 = 1. dpd0 d a t a pointer 0 decrement. when s et, inc dptr in s tr u ction s t a rgeted to dptr0 will decrement dptr0. when cle a red, inc dptr in s tr u ction s will increment dptr0. dpd0 a l s o determine s the direction of au to- u pd a te for dptr0 when dpu0 = 1. s igen s ign a t u re en ab le. when s igen = 1 a ll movc @dptr in s tr u ction s a nd a ll iap a cce ss e s will t a rget the s ign a t u re a rr a y memory. when s igen = 0, a ll movc a nd iap a cce ss e s t a rget code memory. dp s d a t a pointer s elect. dp s s elect s the a ctive d a t a pointer for in s tr u ction s th a t reference dptr. when dp s = 0, dptr will t a rget dptr0 a nd /dptr will t a rget dptr1. when dp s = 1, dptr will t a rget dptr1 a nd /dptr will t a rget dptr0. table 5-4. d a t a pointer a u to-upd a te dpd1 dpd0 update operation for movx and movc (dpu1 = 1 & dpu0 = 1) dps = 0 dps = 1 dptr /dptr dptr /dptr 0 0 dptr0++ dptr1++ dptr1++ dptr0++ 0 1 dptr0-- dptr1++ dptr1++ dptr0-- 1 0 dptr0++ dptr1-- dptr1-- dptr0++ 1 1 dptr0-- dptr1-- dptr1-- dptr0--
29 3709c?micro?5/11 at89lp51/52 - preliminary 6. system clock the s y s tem clock i s gener a ted directly from one of three s elect ab le clock s o u rce s . the three s o u rce s a re the on-chip cry s t a l o s cill a tor, extern a l clock s o u rce, a nd intern a l rc o s cill a tor. a di a - gr a m of the clock subs y s tem i s s hown in fig u re 6-1 . the on-chip cry s t a l o s cill a tor m a y a l s o b e config u red for low or high power oper a tion. the clock s o u rce i s s elected b y the clock s o u rce u s er f us e s as s hown in t ab le 6-1 . s ee ?u s er config u r a tion f us e s ? on p a ge 8 6 . by def au lt, in f as t mode no intern a l clock divi s ion i s us ed to gener a te the cpu clock from the s y s tem clock. in comp a ti b ility mode the def au lt i s to divide the o s cill a tor o u tp u t b y two. the s y s tem clock divider m a y b e us ed to pre s c a le the s y s tem clock with other v a l u e s . the choice of clock s o u rce a l s o a ffect s the s t a rt- u p time a fter a por, bod or power-down event ( s ee ?re s et? on p a ge 32 or ?power-down mode? on p a ge 35 ) figure 6-1. clock subs y s tem di a gr a m 6.1 crystal oscillator when en ab led, the intern a l inverting o s cill a tor a mplifier i s connected b etween xtal1 a nd xtal2 for connection to a n extern a l q ua rtz cry s t a l or cer a mic re s on a tor. the o s cill a tor m a y oper a te in either high-power or low-power mode. low- s peed mode i s intended for cry s t a l s of 12 mhz or le ss a nd con su me s le ss power th a n the higher s peed mode. the config u r a tion as s hown in fig u re 6-2 a pplie s for b oth high a nd low power o s cill a tor s . note th a t in s ome c as e s , extern a l c a p a citor s c1 a nd c2 m a y not b e req u ired d u e to the on-chip c a p a cit a nce of the xtal1 a nd xtal2 inp u t s ( a pproxim a tely 10 pf e a ch). when us ing the cry s t a l o s cill a tor, p4.6 a nd p4.7 will h a ve their inp u t s a nd o u tp u t s di sab led. al s o, xtal2 in cry s t a l o s cill a tor mode s ho u ld not b e us ed to directly drive a b o a rd-level clock witho u t a bu ffer. table 6-1. clock s o u rce s etting s clock source fuse 1 clock source fuse 0 selected clock source 1 1 high power cry s t a l o s cill a tor (f > 12 mhz) 1 0 low power cry s t a l o s cill a tor (f 12 mhz) 01extern a l clock on xtal1 0 0 intern a l 1. 8 432 mhz a u xili a ry o s cill a tor clk osc xtal1 xtal2 system clock (clk sys ) internal 1.84 3 2mhz osc 0 1 2 3 clk osc /2 clk osc /4 clk osc /8 clk osc /1 6 clk osc / 3 2 5-bit clock divider clk irc clk ext clk xtal 0 12345 cdv 2-0 clock fuses 4-bit prescaler tps 3 -0 timer 0 timer 1 timer 2 watchdog
30 3709c?micro?5/11 at89lp51/52 - preliminary an option a l 5 m on-chip re s i s tor c a n b e connected b etween xtal1 a nd gnd. thi s re s i s tor c a n improve the s t a rt u p ch a r a cteri s tic s of the o s cill a tor e s peci a lly a t higher freq u encie s . the re s i s tor c a n b e en ab led/di sab led with the r1 u s er f us e ( s ee ?u s er config u r a tion f us e s ? on p a ge 8 6. ) figure 6-2. cry s t a l o s cill a tor connection s note: 1. c1, c2 = 5 pf 5pf for cry s t a l s =5 pf 5pf for cer a mic re s on a tor s 6.2 external clock source the extern a l clock option di sab le s the o s cill a tor a mplifier a nd a llow s xtal1 to b e driven directly b y a n extern a l clock s o u rce as s hown in fig u re 6-3 . xtal2 m a y b e left u nconnected, us ed as gener a l p u rpo s e i/o p4.7, or config u red to o u tp u t a divided ver s ion of the s y s tem clock. figure 6-3. extern a l clock drive config u r a tion 6.3 internal rc oscillator the at 8 9lp51/52 h as a n intern a l a u xili a ry o s cill a tor t u ned to 1. 8 432 mhz 2.0%. when en ab led as the clock s o u rce, xtal1 a nd xtal2 m a y b e us ed as p4.6 a nd p4.7 re s pectively. ~10 pf ~10 pf c2 c1 r1 ~5 m () ()
31 3709c?micro?5/11 at89lp51/52 - preliminary 6.4 system clock divider the cdv 2-0 b it s in clkreg a llow the s y s tem clock to b e divided down from the s elected clock s o u rce b y power s of 2. the clock divider provide s us er s with a gre a ter freq u ency r a nge when us ing the intern a l o s cill a tor. for ex a mple, to a chieve a 230.4 khz s y s tem freq u ency when us ing the rc o s cill a tor, cdv 2-0 s ho u ld b e s et to 011b for divide- b y- 8 oper a tion. the divider c a n a l s o b e us ed to red u ce power con su mption b y decre as ing the oper a tion a l freq u ency d u ring non-criti- c a l period s . the re su lting s y s tem freq u ency i s given b y the following eq ua tion: where f o s c i s the freq u ency of the s elected clock s o u rce. the clock divider will pre s c a le the clock for the cpu a nd a ll peripher a l s . the v a l u e of cdv m a y b e ch a nged a t a ny time witho u t interr u pt- ing norm a l exec u tion. ch a nge s to cdv a re s ynchronized su ch th a t the s y s tem clock will not p ass thro u gh intermedi a te freq u encie s . when cdv i s u pd a ted, the new freq u ency will t a ke a ffect within a m a xim u m period of 32 x t o s c . in comp a ti b ility mode the divider def au lt s to divide- b y-2 a nd a nd in f as t mode it def au lt s to no divi s ion. note: the re s et v a l u e of clkreg i s 0000000b in f as t mode a nd 01010010b in comp a ti b ility mode. f s y s f o s c 2 cdv ------------ - = table 6-2. clkreg ? clock control regi s ter clkreg = 8 fh re s et v a l u e = 0?0? 00?0b not bit addre ssab le tp s 3tp s 2tp s 1tp s 0 cdv2 cdv1 cdv0 ? bit76543210 symbol function tp s [3-0] timer pre s c a ler. the timer pre s c a ler s elect s the time bas e for timer 0, timer 1, timer 2 a nd the w a tchdog timer. the pre s c a ler i s implemented as a 4- b it b in a ry down co u nter. when the co u nter re a che s zero it i s relo a ded with the v a l u e s tored in the tp s b it s to give a divi s ion r a tio b etween 1 a nd 16. by def au lt the timer s will co u nt every clock cycle in f as t mode (tp s = 0000b) a nd every s ix cycle s in comp a ti b ility mode (tp s = 0101b). cdv[2-0] s y s tem clock divi s ion. determine s the freq u ency of the s y s tem clock rel a tive to the o s cill a tor clock s o u rce. cdiv2 cdiv1 cdiv0 s y s tem clock freq u ency 000f o s c /1 001f o s c /2 010f o s c /4 011f o s c / 8 100f o s c /16 101f o s c /32 110re s erved 111re s erved
32 3709c?micro?5/11 at89lp51/52 - preliminary 7. reset d u ring re s et, a ll i/o regi s ter s a re s et to their initi a l v a l u e s , the port pin s a re s et to their def au lt mode, a nd the progr a m s t a rt s exec u tion from the re s et vector, 0000h. the at 8 9lp51/52 h as five s o u rce s of re s et: power-on re s et, b rown-o u t re s et, extern a l re s et, w a tchdog re s et, a nd s oft- w a re re s et. 7.1 power-on reset a power-on re s et (por) i s gener a ted b y a n on-chip detection circ u it. the detection level v por i s nomin a lly 1.4v. the por i s a ctiv a ted whenever v dd i s b elow the detection level. the por cir- c u it c a n b e us ed to trigger the s t a rt- u p re s et or to detect a m a jor su pply volt a ge f a il u re. the por circ u it en su re s th a t the device i s re s et from power-on. a power-on s eq u ence i s s hown in fig u re 7-1 . when v dd re a che s the power-on re s et thre s hold volt a ge v por , a n initi a liz a tion s eq u ence l as ting t por i s s t a rted. when the initi a liz a tion s eq u ence complete s , the s t a rt- u p timer determine s how long the device i s kept in por a fter v dd ri s e. the s t a rt- u p timer doe s not b egin co u nting u ntil a fter v dd re a che s the brown-o u t detector (bod) thre s hold volt a ge v bod . the por s ign a l i s a ctiv a ted a g a in, witho u t a ny del a y, when v dd f a ll s b elow the por thre s hold level. a power-on re s et (i.e. a cold re s et) will s et the pof fl a g in pcon. the intern a lly gener a ted re s et c a n b e extended b eyond the power-on period b y holding the r s t pin a ctive longer th a n the time-o u t. figure 7-1. power-on re s et s eq u ence note: t por i s a pproxim a tely 143 s 5%. the s t a rt- u p timer del a y i s us er-config u r ab le with the s t a rt- u p time u s er f us e s a nd depend s on the clock s o u rce ( t ab le 7-1 ). the s t a rt-up time f us e s a l s o control the length of the s t a rt- u p time a fter a brown-o u t re s et or when w a king u p from power-down d u ring intern a lly timed mode. the s t a rt- u p del a y s ho u ld b e s elected to provide eno u gh s ettling time for v dd a nd the s elected clock s o u rce. the device oper a ting environment ( su pply volt a ge, freq u ency, temper a t u re, etc.) m us t meet the minim u m s y s tem req u irement s b efore the device exit s re s et a nd s t a rt s norm a l oper a - tion. the r s t pin m a y b e held a ctive extern a lly u ntil the s e condition s a re met. v dd r s t time-o u t t por t rhd v por intern a l re s et r s t intern a l re s et v il t s ut v bod (r s t tied to gnd) (r s t controlled extern a lly) pol (pol tied to vcc)
33 3709c?micro?5/11 at89lp51/52 - preliminary 7.2 brown-out reset the at 8 9lp51/52 h as a n on-chip brown-o u t detection (bod) circ u it for monitoring the v dd level d u ring oper a tion b y comp a ring it to a fixed trigger level. the trigger level v bod for the bod i s nomin a lly 2.0v. the p u rpo s e of the bod i s to en su re th a t if v dd f a il s or dip s while exec u ting a t s peed, the s y s tem will gr a cef u lly enter re s et witho u t the po ss i b ility of error s ind u ced b y incorrect exec u tion. a bod s eq u ence i s s hown in fig u re 7-2 . when v dd decre as e s to a v a l u e b elow the trigger level v bod , the intern a l re s et i s immedi a tely a ctiv a ted. when v dd incre as e s ab ove the trigger level pl us ab o u t 200 mv of hy s tere s i s , the s t a rt- u p timer rele as e s the intern a l re s et a fter the s pecified time-o u t period h as expired ( t ab le 7-1 ). figure 7-2. brown-o u t detector re s et the at 8 9lp51/52 a llow s for a wide v dd oper a ting r a nge. the on-chip bod m a y not b e su ffi- cient to prevent incorrect exec u tion if v bod i s lower th a n the minim u m req u ired v dd r a nge, su ch as when a 5.0v su pply i s co u pled with high freq u ency oper a tion. in su ch c as e s a n extern a l brown-o u t re s et circ u it connected to the r s t pin m a y b e req u ired. 7.3 external reset the r s t pin of the at 8 9lp51/52 c a n f u nction as either a n a ctive-low re s et inp u t or as a n a ctive- high re s et inp u t. the pol a rity of the r s t pin i s s elect ab le us ing the pol pin (formerly ea ). when pol i s high the r s t pin i s a ctive high with a n on-chip p u ll-down re s i s tor tied to gnd. when pol i s low the r s t pin i s a ctive low with a n on-chip p u ll- u p re s i s tor tied to v dd . the r s t pin s tr u ct u re i s s hown in fig u re 7-3 . in comp a ti b ility mode the re s et pin i s sa mpled every s ix clock cycle s a nd m us t b e held a ctive for a t le as t twelve clock cycle s to trigger the intern a l re s et. in f as t mode the re s et pin i s sa mpled every clock cycle a nd m us t b e held a ctive for a t le as t two clock cycle s to trigger the intern a l re s et. table 7-1. s t a rt- u p timer s etting s sut fuse 1 sut fuse 0 clock source t sut ( 5%) s 00 intern a l rc/extern a l clock 16 cry s t a l o s cill a tor 1024 01 intern a l rc/extern a l clock 512 cry s t a l o s cill a tor 204 8 10 intern a l rc/extern a l clock 1024 cry s t a l o s cill a tor 4096 11 intern a l rc/extern a l clock 4096 cry s t a l o s cill a tor 163 8 4 v dd time-o u t v por intern a l re s et t s ut v bod
34 3709c?micro?5/11 at89lp51/52 - preliminary the at 8 9lp51/52 incl u de s a n on-chip power-on re s et a nd brown-o u t detector circ u it th a t en su re s th a t the device i s re s et from s y s tem power u p. in mo s t c as e s a rc s t a rt u p circ u it i s not req u ired on the r s t pin, red u cing s y s tem co s t, a nd the r s t pin m a y b e left u nconnected if a b o a rd-level re s et i s not pre s ent. note: r s t a l s o s erve s as the in- s y s tem progr a mming (i s p) en ab le. i s p i s en ab led when the extern a l re s et pin i s held a ctive. when i s p i s di sab led b y f us e, i s p m a y only b e entered b y p u lling r s t a ctive d u ring power- u p. if thi s b eh a vior i s nece ssa ry, it i s recommended to us e a n a ctive-low re s et s o th a t i s p c a n b e entered b y s horting r s t to gnd a t power- u p. figure 7-3. re s et pin s tr u ct u re 7.4 watchdog reset when the w a tchdog time s o u t, it will gener a te a re s et p u l s e l as ting 49 clock cycle s . by def au lt thi s p u l s e i s a l s o o u tp u t on the r s t pin. to di sab le the r s t o u tp u t the di s rto b it in auxr (comp a ti b ility mode) or wdtcon (f as t mode) m us t b e s et to one. w a tchdog re s et will s et the wdtovf fl a g in wdtcon. to prevent a w a tchdog re s et, the w a tchdog re s et s eq u ence 1eh/e1h m us t b e written to wdtr s t b efore the w a tchdog time s o u t. s ee ?progr a mm ab le w a tchdog timer? on p a ge 73. for det a il s on the oper a tion of the w a tchdog. 7.5 software reset the cpu m a y gener a te a 49-clock cycle re s et p u l s e b y writing the s oftw a re re s et s eq u ence 5ah/a5h to the wdr s t regi s ter. a s oftw a re re s et will s et the s wr s t b it in wdtcon. s ee ? s oftw a re re s et? on p a ge 73 for more inform a tion on s oftw a re re s et. writing a ny s eq u ence s other th a n 5ah/a5h or 1eh/e1h to wdtr s t will gener a te a n immedi a te re s et a nd s et b oth wdtovf a nd s wr s t to fl a g a n error. s oftw a re re s et will a l s o drive the r s t pin a ctive u nle ss di s rto i s s et. 8. power saving modes the at 8 9lp51/52 su pport s two different power-red u cing mode s : idle a nd power-down. the s e mode s a re a cce ss ed thro u gh the pcon regi s ter. addition a l s tep s m a y b e req u ired to a chieve the lowe s t po ss i b le power con su mption while us ing the s e mode s . 8.1 idle mode s etting the idl b it in pcon enter s idle mode. idle mode h a lt s the intern a l cpu clock. the cpu s t a te i s pre s erved in it s entirety, incl u ding the ram, s t a ck pointer, progr a m co u nter, progr a m s t a t us word, a nd a cc u m u l a tor. the port pin s hold the logic s t a te s they h a d a t the time th a t idle w as a ctiv a ted. idle mode le a ve s the peripher a l s r u nning in order to a llow them to w a ke u p the v cc disrto wdt reset rst internal reset pol = 1 v cc disrto wdt reset rst internal reset pol = 0
35 3709c?micro?5/11 at89lp51/52 - preliminary cpu when a n interr u pt i s gener a ted. the timer a nd uart peripher a l s contin u e to f u nction d u r- ing idle. if the s e f u nction s a re not needed d u ring idle, they s ho u ld b e explicitly di sab led b y cle a ring the a ppropri a te control b it s in their re s pective s fr s . the w a tchdog m a y b e s electively en ab led or di sab led d u ring idle b y s etting/cle a ring the wdidle b it. the brown-o u t detector i s a lw a y s a ctive d u ring idle. any en ab led interr u pt s o u rce or re s et m a y termin a te idle mode. when exiting idle mode with a n interr u pt, the interr u pt will immedi a tely b e s erviced, a nd following reti the next in s tr u ction to b e exec u ted will b e the one following the in s tr u ction th a t p u t the device into idle. the power con su mption d u ring idle mode c a n b e f u rther red u ced b y pre s c a ling down the s y s tem clock us ing the s y s tem clock divider ( s ection 6.4 on p a ge 31 ). be a w a re th a t the clock divider will a ffect a ll peripher a l f u nction s a nd bau d r a te s m a y need to b e a dj us ted to m a int a in their r a te with the new clock freq u ency. . 8.2 power-down mode s etting the power-down (pd) b it in pcon enter s power-down mode. power-down mode s top s the o s cill a tor, di sab le s the bod a nd power s down the fl as h memory in order to minimize power con su mption. only the power-on circ u itry will contin u e to dr a w power d u ring power-down. d u r- ing power-down, the power su pply volt a ge m a y b e red u ced to the ram keep- a live volt a ge. the ram content s will b e ret a ined, bu t the s fr content s a re not g ua r a nteed once v dd h as b een red u ced. power-down m a y b e exited b y extern a l re s et, power-on re s et, or cert a in en ab led interr u pt s . table 8-1. pcon ? power control regi s ter pcon = 8 7h re s et v a l u e = 000x 0000b not bit addre ssab le s mod1 s mod0 pwdex pof gf1 gf0 pd idl bit76543210 symbol function s mod1 do ub le b au d r a te b it. do ub le s the bau d r a te of the uart in mode s 1, 2, or 3. s mod0 fr a me error s elect. when s mod0 = 1, s con.7 i s s m0. when s mod0 = 1, s con.7 i s fe. note th a t fe will b e s et a fter a fr a me error reg a rdle ss of the s t a te of s mod0. pwdex power-down exit mo de. when pwdex = 0, w a ke u p from power-down i s extern a lly controlled. when pwdex = 1, w a ke u p from power-down i s intern a lly timed. pof power off fl a g. pof i s s et to ?1? d u ring power u p (i.e. cold re s et). it c a n b e s et or re s et u nder s oftw a re control a nd i s not a ffected b y r s t or bod (i.e. w a rm re s et s ). gf1, gf0 gener a l-p u rpo s e fl a g s pd power-down b it. s etting thi s b it a ctiv a te s power-down oper a tion. the pd b it i s cle a red au tom a tic a lly b y h a rdw a re when w a king u p from power-down. idl idle mode b it. s etting thi s b it a ctiv a te s idle mode oper a tion. the idl b it i s cle a red au tom a tic a lly b y h a rdw a re when w a king u p from idle
36 3709c?micro?5/11 at89lp51/52 - preliminary 8.2.1 interrupt recovery from power-down two extern a l interr u pt s o u rce s m a y b e config u red to termin a te power-down mode: extern a l interr u pt s int0 (p3.2) a nd int1 (p3.3). to w a ke u p b y extern a l interr u pt int0 or int1 , th a t inter- r u pt m us t b e en ab led b y s etting ex0 or ex1 in ie a nd m us t b e config u red for level- s en s itive oper a tion b y cle a ring it0 or it1. when termin a ting power-down b y a n interr u pt, two different w a ke- u p mode s a re a v a il ab le. when pwdex in pcon i s one, the w a ke- u p period i s intern a lly timed as s hown in fig u re 8 -1 . at the f a lling edge on the interr u pt pin, power-down i s exited, the o s cill a tor i s re s t a rted, a nd a n intern a l timer b egin s co u nting. the intern a l clock will not b e a llowed to prop a g a te to the cpu u ntil a fter the timer h as timed o u t. after the time-o u t period the interr u pt s ervice ro u tine will b egin. the time-o u t period i s controlled b y the s t a rt- u p timer f us e s ( s ee t ab le 7-1 on p a ge 33 ). the interr u pt pin need not rem a in low for the entire time-o u t period. figure 8-1. interr u pt recovery from power-down (pwdex = 1) when pwdex = ?0?, the w a ke- u p period i s controlled extern a lly b y the interr u pt. ag a in, a t the f a lling edge on the interr u pt pin, power-down i s exited a nd the o s cill a tor i s re s t a rted. however, the intern a l clock will not prop a g a te u ntil the ri s ing edge of the interr u pt pin as s hown in fig u re 8 - 2 . the interr u pt pin s ho u ld b e held low long eno u gh for the s elected clock s o u rce to s t ab ilize. after the ri s ing edge on the pin the interr u pt s ervice ro u tine will b e exec u ted. figure 8-2. interr u pt recovery from power-down (pwdex = 0) 8.2.2 reset recovery from power-down the w a ke- u p from power-down thro u gh a n extern a l re s et i s s imil a r to the interr u pt with pwdex = ?1?. at the ri s ing edge of r s t, power-down i s exited, the o s cill a tor i s re s t a rted, a nd a n intern a l timer b egin s co u nting as s hown in fig u re 8 -3 . the intern a l clock will not b e a llowed to prop a g a te to the cpu u ntil a fter the timer h as timed o u t. the time-o u t period i s controlled b y the s t a rt- u p timer f us e s . ( s ee t ab le 7-1 on p a ge 33 ). if r s t ret u rn s low b efore the time-o u t, a two clock cycle intern a l re s et i s gener a ted when the intern a l clock re s t a rt s . otherwi s e, the device will rem a in in re s et u ntil r s t i s b ro u ght low. pwd int1 xtal1 t s ut intern a l clock pwd int1 xtal1 intern a l clock
37 3709c?micro?5/11 at89lp51/52 - preliminary figure 8-3. re s et recovery from power-down (pol = 1) 8.3 reducing power consumption s ever a l po ss i b ilitie s need con s ider a tion when trying to red u ce the power con su mption in a n 8 051- bas ed s y s tem. gener a lly, idle or power-down mode s ho u ld b e us ed as often as po ss i b le. all u nneeded f u nction s s ho u ld b e di sab led. the s y s tem clock divider c a n s c a le down the oper- a ting freq u ency d u ring period s of low dem a nd. the ale o u tp u t c a n b e di sab led b y s etting di s ale in auxr, there b y a l s o red u cing emi. 9. interrupts the at 8 9lp51/52 provide s 6 interr u pt s o u rce s : two extern a l interr u pt s , three timer interr u pt s , a nd a s eri a l port interr u pt. the s e interr u pt s a nd the s y s tem re s et e a ch h a ve a s ep a r a te progr a m vector a t the s t a rt of the progr a m memory s p a ce. e a ch interr u pt s o u rce c a n b e individ ua lly en ab led or di sab led b y s etting or cle a ring a b it in the interr u pt en ab le regi s ter ie. the ie regi s ter a l s o cont a in s a glo ba l di sab le b it, ea, which di sab le s a ll interr u pt s . e a ch interr u pt s o u rce c a n b e individ ua lly progr a mmed to one of fo u r priority level s b y s etting or cle a ring b it s in the interr u pt priority regi s ter s ip a nd iph. ip hold s the low order priority b it s a nd iph hold s the high priority b it s for e a ch interr u pt. an interr u pt s ervice ro u tine in progre ss c a n b e interr u pted b y a higher priority interr u pt, bu t not b y a nother interr u pt of the sa me or lower priority. the highe s t priority interr u pt c a nnot b e interr u pted b y a ny other interr u pt s o u rce. if two req u e s t s of different priority level s a re pending a t the end of a n in s tr u ction, the req u e s t of higher priority level i s s erviced. if req u e s t s of the sa me priority level a re pending a t the end of a n in s tr u ction, a n intern a l polling s eq u ence determine s which req u e s t i s s erviced. the polling s eq u ence i s bas ed on the vector a ddre ss ; a n interr u pt with a lower vector a ddre ss h as higher priority th a n a n inter- r u pt with a higher vector a ddre ss . note th a t the polling s eq u ence i s only us ed to re s olve pending req u e s t s of the sa me priority level. the extern a l interr u pt s int0 a nd int1 c a n e a ch b e either level- a ctiv a ted or edge- a ctiv a ted, depending on b it s it0 a nd it1 in regi s ter tcon. the fl a g s th a t a ct ua lly gener a te the s e inter- r u pt s a re the ie0 a nd ie1 b it s in tcon. when the s ervice ro u tine i s vectored to, h a rdw a re cle a r s the fl a g th a t gener a ted a n extern a l interr u pt only if the interr u pt w as edge- a ctiv a ted. if the inter- r u pt w as level a ctiv a ted, then the extern a l req u e s ting s o u rce (r a ther th a n the on-chip h a rdw a re) control s the req u e s t fl a g. the timer 0 a nd timer 1 interr u pt s a re gener a ted b y tf0 a nd tf1, which a re s et b y a rollover in their re s pective timer/co u nter regi s ter s (except for timer 0 in mode 3). when a timer interr u pt i s gener a ted, the on-chip h a rdw a re cle a r s the fl a g th a t gener a ted it when the s ervice ro u tine i s pwd r s t xtal1 t s ut intern a l clock intern a l re s et
38 3709c?micro?5/11 at89lp51/52 - preliminary vectored to. the timer 2 interr u pt i s gener a ted b y a logic or of b it s tf2 a nd exf2 in regi s ter t2con. neither of the s e fl a g s i s cle a red b y h a rdw a re when the cpu vector s to the s ervice ro u - tine. the s ervice ro u tine norm a lly m us t determine whether tf2 or exf2 gener a ted the interr u pt a nd th a t b it m us t b e cle a red b y s oftw a re. the s eri a l port interr u pt i s gener a ted b y the logic or of ri a nd ti in s con. neither of the s e fl a g s i s cle a red b y h a rdw a re when the cpu vector s to the s ervice ro u tine. the s ervice ro u tine norm a lly m us t determine whether ri or ti gener a ted the interr u pt a nd th a t b it m us t b e cle a red b y s oftw a re. all of the b it s th a t gener a te interr u pt s c a n b e s et or cle a red b y s oftw a re, with the sa me re su lt as tho u gh they h a d b een s et or cle a red b y h a rdw a re. th a t i s , interr u pt s c a n b e gener a ted a nd pending interr u pt s c a n b e c a nceled in s oftw a re. 9.1 interrupt response time the interr u pt fl a g s m a y b e s et b y their h a rdw a re in a ny clock cycle. the interr u pt controller poll s the fl a g s in the l as t clock cycle of the in s tr u ction in progre ss . if one of the fl a g s w as s et in the preceding cycle, the po lling cycle will find it a nd the interr u pt s y s tem will gener a te a n lcall to the a ppropri a te s ervice ro u tine as the next in s tr u ction, provided th a t the interr u pt i s not b locked b y a ny of the following condition s : a n interr u pt of eq ua l or higher priority level i s a lre a dy in prog- re ss ; the in s tr u ction in progre ss i s reti or a ny write to the ie, ip or iph regi s ter s ; the cpu i s c u rrently forced into idle b y a n iap or fdata write. e a ch of the s e condition s will b lock the gen- er a tion of the lcall to the interr u pt s ervice ro u tine. the s econd condition en su re s th a t if the in s tr u ction in progre ss i s reti or a ny a cce ss to ie, ip or iph, then a t le as t one more in s tr u ction will b e exec u ted b efore a ny interr u pt i s vectored to. the polling cycle i s repe a ted a t the l as t cycle of e a ch in s tr u ction, a nd the v a l u e s polled a re the v a l u e s th a t were pre s ent a t the previo us clock cycle. if a n a ctive interr u pt fl a g i s not b eing s erviced b ec aus e of one of the ab ove condition s a nd i s no longer a ctive when the b locking condition i s removed, the denied interr u pt will not b e s er- viced. in other word s , the f a ct th a t the interr u pt fl a g w as once a ctive bu t not s erviced i s not remem b ered. every polling cycle i s new. if a req u e s t i s a ctive a nd condition s a re met for it to b e a cknowledged, a h a rdw a re sub ro u tine c a ll to the req u e s ted s ervice ro u tine will b e the next in s tr u ction exec u ted. the c a ll it s elf t a ke s fo u r cycle s . th us , a minim u m of five complete clock cycle s el a p s ed b etween a ctiv a tion of a n interr u pt req u e s t a nd the b eginning of exec u tion of the fir s t in s tr u ction of the s ervice ro u tine. a longer re s pon s e time re su lt s if the req u e s t i s b locked b y one of the previo us ly li s ted condition s . if a n interr u pt of eq ua l or higher priority level i s a lre a dy in progre ss , the a ddition a l w a it time depend s on the n a t u re of the other interr u pt' s s ervice ro u tine. if the in s tr u ction in progre ss i s not in it s fin a l clock cycle, the a ddition a l w a it time c a nnot b e more th a n 4 cycle s , s ince the longe s t table 9-1. interr u pt vector addre ss e s interrupt source vector address s y s tem re s et r s t or por or bod 0000h extern a l interr u pt 0 ie0 0003h timer 0 overflow tf0 000bh extern a l interr u pt 1 ie1 0013h timer 1 overflow tf1 001bh s eri a l port interr u pt ri or ti 0023h timer 2 interr u pt tf2 or exf2 002bh
39 3709c?micro?5/11 at89lp51/52 - preliminary in s tr u ction i s 5 cycle s long. if the in s tr u ction in progre ss i s reti, the a ddition a l w a it time c a nnot b e more th a n 9 cycle s ( a m a xim u m of 4 more cycle s to complete the in s tr u ction in progre ss , pl us a m a xim u m of 5 cycle s to complete the next in s tr u ction). th us , in a s ingle-interr u pt s y s tem, the re s pon s e time i s a lw a y s more th a n 5 clock cycle s a nd le ss th a n 14 clock cycle s . s ee fig u re 9-1 a nd fig u re 9-2 . figure 9-1. minim u m interr u pt re s pon s e time (f as t mode) figure 9-2. m a xim u m interr u pt re s pon s e time (f as t mode) figure 9-3. minim u m interr u pt re s pon s e time (comp a ti b ility mode) figure 9-4. m a xim u m interr u pt re s pon s e time (comp a ti b ility mode) clock cycle s int0 ie0 15 in s tr u ction lcall 1 s t i s r in s tr. c u r. in s tr. ack. clock cycle s int0 ie0 1 14 in s tr u ction reti movx @/dptr, a lcall 1 s t i s r in s tr. ack. 510 clock cycle s int0 ie0 1 in s tr u ction lcall i s r ack. 14 clock cycle s int0 ie0 1 in s tr u ction reti mul ab lcall i s r ack. 13 37 49
40 3709c?micro?5/11 at89lp51/52 - preliminary table 9-2. ie ? interr u pt en ab le regi s ter ie = a 8 h re s et v a l u e = 0000 0000b bit addre ssab le ea ? et2 e s et1 ex1 et0 ex0 bit76543210 symbol function ea glo ba l en ab le/di sab le. all interr u pt s a re di sab led when ea = 0. when ea = 1, e a ch interr u pt s o u rce i s en ab led/di sab led b y s etting /cle a ring it s own en ab le b it. et2 timer 2 interr u pt en ab le e ss eri a l port interr u pt en ab le et1 timer 1 interr u pt en ab le ex1 extern a l interr u pt 1 en ab le et0 timer 0 interr u pt en ab le ex0 extern a l interr u pt 0 en ab le table 9-3. ip ? interr u pt priority regi s ter ip = b 8 h re s et v a l u e = 0000 0000b bit addre ssab le ?? pt2 p s pt1 px1 pt0 px0 bit76543210 symbol function pt2 timer 2 interr u pt priority low p ss eri a l port interr u pt priority low pt1 timer 1 interr u pt priority low px1 extern a l interr u pt 1 priority low pt0 timer 0 interr u pt priority low px0 extern a l interr u pt 0 priority low table 9-4. iph ? interr u pt priority high regi s ter iph = b7h re s et v a l u e = 0000 0000b not bit addre ssab le ?? pt2h p s h pt1h px1h pt0h px0h bit76543210 symbol function pt2h timer 2 interr u pt priority high p s h s eri a l port interr u pt priority high pt1h timer 1 interr u pt priority high px1h extern a l interr u pt 1 priority high pt0h timer 0 interr u pt priority high px0h extern a l interr u pt 0 priority high
41 3709c?micro?5/11 at89lp51/52 - preliminary 10. i/o ports the at 8 9lp51/52 c a n b e config u red for b etween 32 a nd 36 i/o pin s . the ex a ct n u m b er of i/o pin s a v a il ab le depend s on the clock, extern a l memory a nd p a ck a ge type as s hown in t ab le 10- 1 . 10.1 port configuration e a ch 8 - b it port on the at 8 9lp51/52 m a y b e config u red in one of fo u r mode s : q uas i- b idirection a l ( s t a nd a rd 8 051 port o u tp u t s ), p us h-p u ll o u tp u t, open-dr a in o u tp u t, or inp u t-only. port mode s m a y b e ass igned in s oftw a re on a port- b y-port bas i s as s hown in t ab le 10-2 us ing the pmod regi s ter li s ted in t ab le 10-3 . the tri s t a te-port u s er f us e determine s the def au lt s t a te of the port pin s ( s ee ?u s er config u r a tion f us e s ? on p a ge 8 6 ). when the f us e i s en ab led, a ll port pin s def au lt to inp u t-only mode a fter re s et. when the f us e i s di sab led, a ll port pin s on p1, p2 a nd p3 def au lt to q uas i- b idirection a l mode a fter re s et a nd a re we a kly p u lled high. p0 i s s et to open-dr a in mode. p4 a lw a y s oper a te s in q uas i- b idirection a l mode. e a ch port pin a l s o h as a s chmitt-triggered inp u t for improved inp u t noi s e rejection. d u ring power-down a ll the s chmitt-triggered inp u t s a re di sab led with the exception of p3.2 (int0 ), p3.3 (int1 ), r s t, p 4 . 6 ( x ta l 1 ) a nd p4.7 (xtal2). therefore, p3.2, p3.3, p4.6 a nd p4.7 s ho u ld not b e left flo a ting d u ring power-down. . table 10-1. i/o pin config u r a tion s clock source external program access external data access number of i/o pins extern a l cry s t a l or re s on a tor ye s (p s en+ale+p0+p2) ye s (rd+wr) 14 no 16 no ye s (ale+rd+wr+p0) 31 no 34 extern a l clock ye s (p s en+ale+p0+p2) ye s (rd+wr) 15 no 17 no ye s (ale+rd+wr+p0) 32 no 35 intern a l rc o s cill a tor ye s (p s en+ale+p0+p2) ye s (rd+wr) 16 no 1 8 no ye s (ale+rd+wr+p0) 33 no 36 table 10-2. config u r a tion mode s for port x pxm0 pxm1 port mode 00q uas i- b idirection a l 01p us h-p u ll o u tp u t 10inp u t only (high imped a nce) 1 1 open-dr a in o u tp u t
42 3709c?micro?5/11 at89lp51/52 - preliminary . 10.1.1 quasi-bidirectional output port pin s in q uas i- b idirection a l o u tp u t mode f u nction s imil a r to s t a nd a rd 8 051 port pin s . a q uas i- b idirection a l port c a n b e us ed b oth as a n inp u t a nd o u tp u t witho u t the need to reconfig u re the port. thi s i s po ss i b le b ec aus e when the port o u tp u t s a logic high, it i s we a kly driven, a llowing a n extern a l device to p u ll the pin low. when the pin i s driven low, it i s driven s trongly a nd ab le to s ink a l a rge c u rrent. there a re three p u ll- u p tr a n s i s tor s in the q uas i- b idirection a l o u tp u t th a t s erve different p u rpo s e s . one of the s e p u ll- u p s , c a lled the ?very we a k? p u ll- u p, i s t u rned on whenever the port l a tch for the pin cont a in s a logic ?1?. thi s very we a k p u ll- u p s o u rce s a very s m a ll c u rrent th a t will p u ll the pin high if it i s left flo a ting. when the pin i s p u lled low extern a lly thi s p u ll- u p will a lw a y s s o u rce s ome c u rrent. a s econd p u ll- u p, c a lled the ?we a k? p u ll- u p, i s t u rned on when the port l a tch for the pin cont a in s a logic ?1? a nd the pin it s elf i s a l s o a t a logic ?1? level. thi s p u ll- u p provide s the prim a ry s o u rce c u rrent for a q uas i- b idirection a l pin th a t i s o u tp u tting a ?1?. if thi s pin i s p u lled low b y a n extern a l device, thi s we a k p u ll- u p t u rn s off, a nd only the very we a k p u ll- u p rem a in s on. in order to p u ll the pin low u nder the s e condition s , the extern a l device h as to s ink eno u gh c u rrent to overpower the we a k p u ll- u p a nd p u ll the port pin b elow it s inp u t thre s hold volt a ge. the third p u ll- u p i s referred to as the ? s trong? p u ll- u p. thi s p u ll- u p i s us ed to s peed u p low-to- high tr a n s ition s on a q uas i- b idirection a l port pin when the port l a tch ch a nge s from a logic ?0? to a logic ?1?. when thi s occ u r s , the s trong p u ll- u p t u rn s on for one cpu clock, q u ickly p u lling the port pin high. the q uas i- b idirection a l port config u r a tion i s s hown in fig u re 10-1 . 10.1.2 input-only mode the inp u t only port config u r a tion i s s hown in fig u re 10-2 . the o u tp u t driver s a re tri s t a ted. the inp u t incl u de s a s chmitt-triggered inp u t for improved inp u t noi s e rejection. the inp u t circ u itry of p3.2, p3.3, p4.6 a nd p4.7 i s not di sab led d u ring power-down ( s ee fig u re 10-3 ) a nd therefore the s e pin s s ho u ld not b e left flo a ting d u ring power-down when config u red in thi s mode. inp u t-only mode c a n red u ce power con su mption for low-level inp u t s over q uas i- b idirection a l mode b ec aus e the ?very we a k? p u ll- u p i s t u rned off a nd only very s m a ll le a k a ge c u rrent in the sub micro a mp r a nge i s pre s ent. table 10-3. pmod ? port mode regi s ter pmod = c1h re s et v a l u e = 0000 0011b not bit addre ssab le p3m1 p3m0 p2m1 p2m0 p1m1 p1m0 p0m1 p0m0 bit76543210 symbol function p3m 1-0 port 3 config u r a tion mode p2m 1-0 port 2 config u r a tion mode p1m 1-0 port 1 config u r a tion mode p0m 1-0 port 0 config u r a tion mode
43 3709c?micro?5/11 at89lp51/52 - preliminary figure 10-1. q uas i- b idirection a l o u tp u t figure 10-2. inp u t only figure 10-3. inp u t circ u it for p3.2, p3.3, p4.6 a nd p4.7 10.1.3 open-drain output the open-dr a in o u tp u t config u r a tion t u rn s off a ll p u ll- u p s a nd only drive s the p u ll-down tr a n s i s tor of the port pin when the port l a tch cont a in s a logic ?0?. to b e us ed as a logic o u tp u t, a port con- fig u red in thi s m a nner m us t h a ve a n extern a l p u ll- u p, typic a lly a re s i s tor tied to v dd . the p u ll- down for thi s mode i s the sa me as for the q uas i- b idirection a l mode. the open-dr a in port config u - r a tion i s s hown in fig u re 10-4 . the inp u t circ u itry of p3.2, p3.3, p4.6 a nd p4.7 i s not di sab led d u ring power-down ( s ee fig u re 10-3 ) a nd therefore the s e pin s s ho u ld not b e left flo a ting d u ring power-down when config u red in thi s mode. figure 10-4. open-dr a in o u tp u t 1 clo c k del a y (d flip-flop) s trong v e r y w e a k w e a k p o r t pin v cc v cc v cc f rom p o r t regi s ter inp u t d a t a pwd p o r t pin inp u t d a t a pwd port pin inp u t d a t a p o r t pin f rom p o r t regi s ter inp u t d a t a pwd
44 3709c?micro?5/11 at89lp51/52 - preliminary 10.1.4 push-pull output the p us h-p u ll o u tp u t config u r a tion h as the sa me p u ll-down s tr u ct u re as b oth the open-dr a in a nd the q uas i- b idirection a l o u tp u t mode s , bu t provide s a contin u o us s trong p u ll- u p when the port l a tch cont a in s a logic ?1?. the p us h-p u ll mode m a y b e us ed when more s o u rce c u rrent i s needed from a port o u tp u t. the p us h-p u ll port config u r a tion i s s hown in fig u re 10-5 . figure 10-5. p us h-p u ll o u tp u t 10.2 port read-modify-write a re a d from a port will re a d either the s t a te of the pin s or the s t a te of the port regi s ter depending on which in s tr u ction i s us ed. s imple re a d in s tr u ction s will a lw a y s a cce ss the port pin s directly. re a d-modify-write in s tr u ction s , which re a d a v a l u e, po ss i b ly modify it, a nd then write it ba ck, will a lw a y s a cce ss the port regi s ter. thi s incl u de s b it write in s tr u ction s su ch as clr or s etb as they a ct ua lly re a d the entire port, modify a s ingle b it, then write the d a t a ba ck to the entire port. s ee t ab le 10-4 for a complete li s t of re a d-modify-write in s tr u ction which m a y a cce ss the port s . p o r t pin v cc f rom p o r t regi s ter inp u t d a t a pwd table 10-4. port re a d-modify-write in s tr u ction s mnemonic instruction example anl logic a l and anl p1, a orl logic a l or orl p1, a xrl logic a l ex-or xrl p1, a jbc j u mp if b it s et a nd cle a r b it jbc p3.0, label cpl complement b it cpl p3.1 inc increment inc p1 dec decrement dec p3 djnz decrement a nd j u mp if not zero djnz p3, label mov px.y, c move c a rry to b it y of port x mov p1.0, c clr px.y cle a r b it y of port x clr p1.1 s etb px.y s et b it y of port x s etb p3.2
45 3709c?micro?5/11 at89lp51/52 - preliminary 10.3 port alternate functions mo s t gener a l-p u rpo s e digit a l i/o pin s of the at 8 9lp51/52 s h a re f u nction a lity with the v a rio us i/o s needed for the peripher a l u nit s . t ab le 10-6 li s t s the a ltern a te f u nction s of the port pin s . altern a te f u nction s a re connected to the pin s in a logic and f as hion. in order to en ab le the a ltern a te f u nction on a port pin, th a t pin m us t h a ve a ?1? in it s corre s ponding port regi s ter b it, otherwi s ethe inp u t/o u tp u t will a lw a y s b e ?0?. however, a ltern a te f u nction s m a y b e tempor a rily forced to ?0? b y cle a ring the ass oci a ted port b it, provided th a t the pin i s not in inp u t-only mode. f u rthermore, e a ch pin m us t b e config u red for the correct inp u t/o u tp u t mode as req u ired b y it s peripher a l b efore it m a y b e us ed as su ch. t ab le 10-5 s how s how to config u re a generic pin for us e with a n a ltern a te f u nction. if two or more port pin s on the sa me 8 - b it req u ire difference direc- tion s , the port m us t b e config u red for b idirection a l oper a tion. table 10-5. pin f u nction config u r a tion s for port x pin y pxm0 pxm1 px.y i/o mode 00 1 b idirection a l (intern a l p u ll- u p) 01 1o u tp u t 10 xinp u t 11 1 b idirection a l (extern a l p u ll- u p) table 10-6. port pin altern a te f u nction s port pin configuration bits alternate function notes pxm0 pxm1 p0.0?p0.7 n/a ad0?ad7 addre ss a nd d a t a on port 0 a re au tom a tic a lly config u red as o u tp u t or inp u t reg a rdle ss of p0m0 a nd p0m1. p1.0 p1m0 p1m1 t2 t2 clock o u t toggle s p1.0 directly p1.1 p1m0 p1m1 t2ex p1.5 p1m0 p1m1 mo s i p1.6 p1m0 p1m1 mi s o p1.7 p1m0 p1m1 s ck p2.0?p2.7 n/a a 8 ?a15 addre ss on port 2 i s au tom a tic a lly config u red as o u tp u t reg a rdle ss of p2m0 a nd p2m1. p3.0 p3m0 p3m1 rxd p3.1 p3m0 p3m1 txd p3.2 p3m0 p3m1 int0 p3.3 p3m0 p3m1 int1 p3.4 p3m0 p3m1 t0 t0 clock o u t toggle s p3.4 directly p3.5 p3m0 p3m1 t1 t1 clock o u t toggle s p3.5 directly p3.6 p3m0 p3m1 wr p3.7 p3m0 p3m1 rd
46 3709c?micro?5/11 at89lp51/52 - preliminary 11. timer 0 and timer 1 the at 8 9lp51/52 h as two 16- b it timer/co u nter s , timer 0 a nd timer 1, with the following fe a t u re s : ? two independent 16- b it timer/co u nter s with 8 - b it relo a d regi s ter s ?uart bau d r a te gener a tion us ing timer 1 ?o u tp u t pin toggle on timer overflow ? s plit timer mode a llow s for three s ep a r a te timer s (2 8 - b it, 1 16- b it) ?g a ted mode s a llow timer s to r u n/h a lt bas ed on a n extern a l inp u t timer 0 a nd timer 1 h a ve s imil a r mode s of oper a tion. a s timer s , the timer regi s ter s norm a lly incre as e every clock cycle. th us , the regi s ter s co u nt clock cycle s . the timer r a te c a n b e pre s - c a led b y a v a l u e b etween 1 a nd 16 us ing the timer pre s c a ler ( s ee t ab le 6-2 on p a ge 31 ). both timer s s h a re the sa me pre s c a ler. in comp a ti b ility mode cdv def au lt s to 2, s o a clock cycle con- s i s t s of two o s cill a tor period s , a nd the pre s c a ler def au lt s to 6 m a king the co u nt r a te eq ua l to 1/12 of the o s cill a tor freq u ency. by def au lt in f as t mode cdv = 0 a nd tp s =0 s o the co u nt r a te i s eq ua l to the o s cill a tor freq u ency. a s co u nter s , the timer regi s ter s a re incremented in re s pon s e to a 1-to-0 tr a n s ition a t the corre- s ponding inp u t pin s , t0 or t1. in f as t mode the extern a l inp u t i s sa mpled every clock cycle. when the sa mple s s how a high in one cycle a nd a low in the next cycle, the co u nt i s incre- mented. the new co u nt v a l u e a ppe a r s in the regi s ter d u ring the cycle following the one in which the tr a n s ition w as detected. s ince 2 clock cycle s a re req u ired to recognize a 1-to-0 tr a n s ition, the m a xim u m co u nt r a te i s 1/2 of the s y s tem freq u ency. there a re no re s triction s on the d u ty cycle of the inp u t s ign a l, bu t it s ho u ld b e held for a t le as t one f u ll clock cycle to en su re th a t a given level i s sa mpled a t le as t once b efore it ch a nge s . in comp a ti b ility mode the co u nter inp u t sa mpling i s controlled b y the pre s c a ler. s ince tp s def au lt s to 6 in thi s mode, the pin s a re sa mpled every s ix s y s tem clock s . therefore the inp u t s ig- n a l s ho u ld b e held for a t le as t s ix clock cycle s to en su re th a t a given level i s sa mpled a t le as t once b efore it ch a nge s . f u rthermore, the timer or co u nter f u nction s for timer 0 a nd timer 1 h a ve fo u r oper a ting mode s : 13- b it timer, 16- b it timer, 8 - b it au to-relo a d timer, a nd s plit timer. the control b it s c/t in the s pe- ci a l f u nction regi s ter tmod s elect the timer or co u nter f u nction. the b it p a ir s (m1, m0) in tmod s elect the oper a ting mode s . table 11-1. timer 0/1 regi s ter su mm a ry name address purpose bit-addressable tcon 88 h control y tmod 8 9h mode n tl0 8 ah timer 0 low- b yte n tl1 8 bh timer 1 low- b yte n th0 8 ch timer 0 high- b yte n th1 8 dh timer 1 high- b yte n tconb 91h mode n
47 3709c?micro?5/11 at89lp51/52 - preliminary 11.1 mode 0 ? 13-bit timer/counter both timer s in mode 0 a re 8 - b it co u nter s with a divide- b y-32 pre s c a ler. fig u re 11-1 s how s the mode 0 oper a tion as it a pplie s to timer 1. a s the co u nt roll s over from a ll ?1? s to a ll ?0? s , it s et s the timer interr u pt fl a g tf1. the co u nter inp u t i s en ab led to the timer when tr1 = 1 a nd either gate1 = 0 or int1 =1. s etting gate1 = 1 a llow s the timer to b e controlled b y extern a l inp u t int1 , to f a cilit a te p u l s e width me asu rement s . tr1 i s a control b it in the s peci a l f u nction regi s - ter tcon. gate1 i s in tmod. the 13- b it regi s ter con s i s t s of a ll 8 b it s of th1 a nd the lower 5 b it s of tl1. the u pper 3 b it s of tl1 a re indetermin a te a nd s ho u ld b e ignored. s etting the r u n fl a g (tr1) doe s not cle a r the regi s ter s . figure 11-1. timer/co u nter 1 mode 0: 13- b it co u nter mode 0 oper a tion i s the sa me for timer 0 as for timer 1, except th a t tr0, tf0, gate0 a nd int0 repl a ce the corre s ponding timer 1 s ign a l s in fig u re 11-1 . there a re two different c/t b it s , one for timer 1 (tmod.6) a nd one for timer 0 (tmod.2). 11.2 mode 1 ? 16-bit timer/counter in mode 1 the timer s a re config u red for 16- b it oper a tion. the timer regi s ter i s r u n with a ll 16 b it s a nd the clock i s a pplied to the com b ined high a nd low timer regi s ter s (th1/tl1). a s clock p u l s e s a re received, the timer co u nt s u p: 0000h, 0001h, 0002h, etc. an overflow occ u r s on the ffffh-to-0000h tr a n s ition, u pon which the overflow fl a g b it in tcon i s s et. s ee fig u re 11-2 . mode 1 oper a tion i s the sa me for timer/co u nter 0. figure 11-2. timer/co u nter 1 mode 1: 16- b it co u nter mode 0: time-o u t period 8 192 s y s tem freq u ency ------------------------------------------------- - tp s 1 + () = o s c t1 pin tr1 gate1 int1 pin tl1 (5 bit s ) control interr u pt c/t = 0 c/t = 1 th1 ( 8 bit s ) tf1 cdv tp s mode 1: time-o u t period 65536 s y s tem freq u ency ------------------------------------------------- - tp s 1 + () = o s c t1 pin tr1 gate1 int1 pin tl1 ( 8 bit s ) control inter r u p t c/t = 0 c/t =1 th1 ( 8 bit s ) tf1 cdv tp s
48 3709c?micro?5/11 at89lp51/52 - preliminary 11.3 mode 2 ? 8-bit auto -reload timer/counter mode 2 config u re s the timer regi s ter as a n 8 - b it co u nter (tl1) with au tom a tic relo a d, as s hown in fig u re 11-3 . overflow from tl1 not only s et s tf1, bu t a l s o relo a d s tl1 with the content s of th1, which i s pre s et b y s oftw a re. the relo a d le a ve s th1 u nch a nged. mode 2 oper a tion i s the sa me for timer/co u nter 0. figure 11-3. timer/co u nter 1 mode 2: 8 - b it a u to-relo a d 11.4 mode 3 ? 8-bit split timer timer 1 in mode 3 s imply hold s it s co u nt. the effect i s the sa me as s etting tr1 = 0. timer 0 in mode 3 e s t ab li s he s tl0 a nd th0 as two s ep a r a te co u nter s . the logic for mode 3 on timer 0 i s s hown in fig u re 11-4 . tl0 us e s the timer 0 control b it s : c/t, gate0, tr0, int0 , a nd tf0. th0 i s locked into a timer f u nction (co u nting clock cycle s ) a nd t a ke s over the us e of tr1 a nd tf1 from timer 1. th us , th0 now control s the timer 1 interr u pt. while timer 0 i s in mode 3, timer 1 will s till o b ey it s s etting s in tmod bu t c a nnot gener a te a n interr u pt. mode 3 i s for a pplic a tion s req u iring a n extr a 8 - b it timer or co u nter. with timer 0 in mode 3, the at 8 9lp51/52 c a n a ppe a r to h a ve fo u r timer/co u nter s . when timer 0 i s in mode 3, timer 1 c a n b e t u rned on a nd off b y s witching it o u t of a nd into it s own mode 3. in thi s c as e, timer 1 c a n s till b e us ed b y the s eri a l port as a bau d r a te gener a tor or in a ny a pplic a tion not req u iring a n interr u pt. figure 11-4. timer/co u nter 0 mode 3: two 8 - b it co u nter s mode 2: time-o u t period 256 th0 ? () s y s tem freq u ency ------------------------------------------------- - tp s 1 + () = o s c t1 pin tr1 gate1 tf1 tl1 ( 8 bit s ) th1 ( 8 bit s ) control relo a d inter r u p t int0 pin c/t = 0 c/t = 1 cdv tp s control inter r up t control inter r up t (8 bits) (8 bits) c/t = 0 c/t =1 t0 pin gate0 int0 pin tps tps cdv osc cdv osc
49 3709c?micro?5/11 at89lp51/52 - preliminary . 11.5 clock output (pin toggle mode) on the at 8 9lp51/52, timer 0 a nd timer 1 m a y b e independently config u red to toggle their re s pective co u nter pin s , t0 a nd t1, on overflow b y s etting the t0oe or t1oe b it s in tconb. the c/tx b it s m us t b e s et to ?0? when in toggle mode a nd the t0 (p3.4) a nd t1 (p3.5) pin s m us t b e config u red in a n o u tp u t mode. the timer overflow fl a g s a nd interr u pt s will contin u e to f u nc- tion while in toggle mode a nd timer 1 m a y s till gener a te the bau d r a te for the uart. the timer gate f u nction a l s o work s in toggle mode, a llowing the o u tp u t to b e h a lted b y a n extern a l inp u t. toggle mode c a n b e us ed with timer mode 2 to o u tp u t a 50% d u ty cycle clock with 8 - b it pro- gr a mm ab le freq u ency. t x i s toggled a t every timer x overflow with the p u l s e width determined b y the v a l u e of thx. an ex a mple w a veform i s given in fig u re 11-5 . the following form u l a give s the o u tp u t freq u ency for timer 0 in mode 2. table 11-2. tcon ? timer/co u nter control regi s ter tcon = 88 h re s et v a l u e = 0000 0000b bit addre ssab le tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 bit76543210 symbol function tf1 timer 1 overflow fl a g. s et b y h a rdw a re on timer/co u nter overflow. cle a red b y h a rdw a re when the proce ss or vector s to interr u pt ro u tine. tr1 timer 1 r u n control b it. s et/cle a red b y s oftw a re to t u rn timer/co u nter on/off. tf0 timer 0 overflow fl a g. s et b y h a rdw a re on timer/co u nter overflow. cle a red b y h a rdw a re when the proce ss or vector s to interr u pt ro u tine. tr0 timer 0 r u n control b it. s et/cle a red b y s oftw a re to t u rn timer/co u nter on/off. ie1 interr u pt 1 edge fl a g. s et b y h a rdw a re when extern a l interr u pt edge detected. cle a red when interr u pt proce ss ed. it1 interr u pt 1 type control b it. s et/cle a red b y s oftw a re to s pecify f a lling edge/low level triggered extern a l interr u pt s . ie0 interr u pt 0 edge fl a g. s et b y h a rdw a re when extern a l interr u pt edge detected. cle a red when interr u pt proce ss ed. it0 interr u pt 0 type control b it. s et/cle a red b y s oftw a re to s pecify f a lling edge/low level triggered extern a l interr u pt s . table 11-3. tconb ? timer/co u nter control regi s ter b tconb = 91h re s et v a l u e = 0000 0000b not bit addre ssab le t1oe t0oe s pen????? bit76543210 symbol function t1oe timer 1 o u tp u t en ab le. config u re s timer 1 to toggle t1 (p3.5) u pon overflow. t0oe timer 0 o u tp u t en ab le. config u re s timer 0 to toggle t0 (p3.4) u pon overflow. s pen en ab le s s pi mode for uart mode 0 mode 2: f out s y s tem freq u ency 2256th0 ? () ------------------------------------------------- - 1 tp s 1 + -------------------- - =
50 3709c?micro?5/11 at89lp51/52 - preliminary figure 11-5. timer 0/1 toggle mode 2 w a veform tx thx ffh table 11-4. tmod ? timer/co u nter mode control regi s ter tmod addre ss = 0 8 9h re s et v a l u e = 0000 0000b not bit addre ssab le gate1 c/t1 t1m1 t1m0 gate0 c/t0 t0m0 t0m1 bit76543210 symbol function gate1 timer 1 g a ting control. when s et, timer/co u nter 1 i s en ab led only while int1 pin i s high a nd tr1 control pin i s s et. when cle a red, timer 1 i s en ab led whenever tr1 control b it i ss et. c/t1 timer or co u nter s elector 1. cle a red for timer oper a tion (inp u t from intern a l s y s tem clock). s et for co u nter oper a tion (inp u t from t1 inp u t pin). c/t1 m us t b e zero when us ing timer 1 in clock o u t mode. t1m1 t1m0 timer 1 oper a ting mode mode t1m1 t1m0 operation 00013- b it timer mode. 8 - b it timer/co u nter th1 with tl1 as 5- b it pre s c a ler. 10116- b it timer mode. th1 a nd tl1 a re c as c a ded to form a 16- b it timer/co u nter. 210 8 - b it a u to relo a d mode. th1 hold s a v a l u e which i s relo a ded into 8 - b it timer/co u nter tl1 e a ch time it overflow s . 311timer/co u nter 1 i s s topped gate0 timer 0 g a ting control. when s et, timer/co u nter 0 i s en ab led only while int0 pin i s high a nd tr0 control pin i s s et. when cle a red, timer 0 i s en ab led whenever tr0 control b it i ss et. c/t0 timer or co u nter s elector 0. cle a red for timer oper a tion (inp u t from intern a l s y s tem clock). s et for co u nter oper a tion (inp u t from t0 inp u t pin). c/t0 m us t b e zero when us ing timer 0 in clock o u t mode. t0m1 t0m0 timer 0 oper a ting mode mode t0m1 t0m0 operation 00013- b it timer mode. 8 - b it timer/co u nter th0 with tl0 as 5- b it pre s c a ler. 10116- b it timer mode. th0 a nd tl0 a re c as c a ded to form a 16- b it timer/co u nter. 210 8 - b it a u to relo a d mode. th0 hold s a v a l u e which i s relo a ded into 8 - b it timer/co u nter tl0 e a ch time it overflow s . 311 s plit timer mode. tl0 i s a n 8 - b it timer/co u nter controlled b y the s t a nd a rd timer 0 control b it s . th0 i s a n 8 - b it timer only controlled b y timer 1 control b it s .
51 3709c?micro?5/11 at89lp51/52 - preliminary 12. timer 2 the at 8 9lp51/52 incl u de s a 16- b it timer/co u nter 2 with the following fe a t u re s : ?16- b it timer/co u nter with one 16- b it relo a d/c a pt u re regi s ter ? one extern a l relo a d/c a pt u re inp u t ? up/down co u nting mode with extern a l direction control ?uart bau d r a te gener a tion ?o u tp u t-pin toggle on timer overflow ?d ua l s lope s ymmetric oper a ting mode s ?timer 2 i s incl u ded in at 8 9lp51, u nlike at 8 9 s 51. timer 2 i s a 16- b it timer/co u nter th a t c a n oper a te as either a timer or a n event co u nter. the type of oper a tion i s s elected b y b it c/t2 in the s fr t2con. timer 2 h as three oper a ting mode s : c a pt u re, au to-relo a d ( u p or down co u nting), a nd bau d r a te gener a tor. the mode s a re s elected b y b it s in t2con a nd t2mod, as s hown in t ab le 12-3 . timer 2 a l s o s erve s as the time bas e for the comp a re/c a pt u re arr a y ( s ee s ection 13. ?extern a l interr u pt s ? on p a ge 57 ). timer 2 con s i s t s of two 8 - b it regi s ter s , th2 a nd tl2. in the timer f u nction, the regi s ter i s incre- mented every clock cycle. s ince a clock cycle con s i s t s of one o s cill a tor period, the co u nt r a te i s eq ua l to the o s cill a tor freq u ency. the timer r a te c a n b e pre s c a led b y a v a l u e b etween 1 a nd 16 us ing the timer pre s c a ler ( s ee t ab le 6-2 on p a ge 31 ). in the co u nter f u nction, the regi s ter i s incremented in re s pon s e to a 1-to-0 tr a n s ition a t it s corre- s ponding extern a l inp u t pin, t2. in thi s f u nction, the extern a l inp u t i s sa mpled every clock cycle. when the sa mple s s how a high in one cycle a nd a low in the next cycle, the co u nt i s incre- mented. the new co u nt v a l u e a ppe a r s in the regi s ter d u ring the cycle following the one in which the tr a n s ition w as detected. s ince two clock cycle s a re req u ired to recognize a 1-to-0 tr a n s ition, the m a xim u m co u nt r a te i s 1/2 of the o s cill a tor freq u ency. to en su re th a t a given level i s sa m- pled a t le as t once b efore it ch a nge s , the level s ho u ld b e held for a t le as t one f u ll clock cycle. the following definition s for timer 2 a re us ed in the subs eq u ent p a r a gr a ph s : table 12-1. timer 2 oper a ting mode s rclk + tclk cp/rl2 dcen t2oe tr2 mode 0000116- b it a u to-relo a d 0010116- b it a u to-relo a d up-down 01x0116- b it c a pt u re 1 xxx1b au d r a te gener a tor xxx11freq u ency gener a tor x x x x 0 (off) table 12-2. timer 2 definition s symbol definition min 0000h max ffffh bottom 16- b it v a l u e of {rcap2h,rcap2l}
52 3709c?micro?5/11 at89lp51/52 - preliminary 12.1 timer 2 registers control a nd s t a t us b it s for timer 2 a re cont a ined in regi s ter s t2con ( s ee t ab le 12-3 ) a nd t2mod ( s ee t ab le 12-4 ). the regi s ter p a ir {th2, tl2} a t a ddre ss e s 0cdh a nd 0cch a re the 16- b it timer regi s ter for timer 2. the regi s ter p a ir {rcap2h, rcap2l} a t a ddre ss e s 0cbh a nd 0cah a re the 16- b it c a pt u re/relo a d regi s ter for timer 2 in c a pt u re a nd au to-relo a d mode s . table 12-3. t2con ? timer/co u nter 2 control regi s ter t2con addre ss = 0c 8 h re s et v a l u e = 0000 0000b bit addre ssab le tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl2 bit76543210 symbol function tf2 timer 2 overflow fl a g s et b y a timer 2 overflow a nd m us t b e cle a red b y s oftw a re. tf2 will not b e s et when either rclk = 1 or tclk = 1. exf2 timer 2 extern a l fl a g s et when either a c a pt u re or relo a d i s c aus ed b y a neg a tive tr a n s ition on t2ex a nd exen2 = 1. when timer 2 interr u pt i s en ab led, exf2 = 1 will c aus e the cpu to vector to the timer 2 interr u pt ro u tine. exf2 m us t b e cle a red b y s oftw a re. exf2 doe s not c aus e a n interr u pt in u p/down co u nter mode (dcen = 1) or d ua l- s lope mode. rclk receive clock en ab le. when s et, c aus e s the s eri a l port to us e timer 2 overflow p u l s e s for it s receive clock in s eri a l port mode s 1 a nd 3. rclk = 0 c aus e s timer 1 overflow s to b e us ed for the receive clock. tclk tr a n s mit clock en ab le. when s et, c aus e s the s eri a l port to us e timer 2 overflow p u l s e s for it s tr a n s mit clock in s eri a l port mode s 1 a nd 3. tclk = 0 c aus e s timer 1 overflow s to b e us ed for the tr a n s mit clock. exen2 timer 2 extern a l en ab le. when s et, a llow s a c a pt u re or relo a d to occ u r as a re su lt of a neg a tive tr a n s ition on t2ex if timer 2 i s not b eing us ed to clock the s eri a l port. exen2 = 0 c aus e s timer 2 to ignore event s a t t2ex. tr2 s t a rt/ s top control for timer 2. tr2 = 1 s t a rt s the timer. c/t2 timer or co u nter s elect for timer 2. c/t2 = 0 for timer f u nction. c/t2 = 1 for extern a l event co u nter (f a lling edge triggered). cp/rl2 c a pt u re/relo a d s elect. cp/rl2 = 1 c aus e s c a pt u re s to occ u r on neg a tive tr a n s ition s a t t2ex if exen2 = 1. cp/rl2 = 0 c aus e s au tom a tic relo a d s to occ u r when timer 2 overflow s or neg a tive tr a n s ition s occ u r a t t2ex when exen2 = 1. when either rclk or tclk = 1, thi s b it i s ignored a nd the timer i s forced to au to-relo a d on timer 2 overflow. table 12-4. t2mod ? timer 2 mode control regi s ter t2mod addre ss = 0c9h re s et v a l u e = 0000 0000b not bit addre ssab le ??????t2oedcen bit76543210 symbol function t2oe timer 2 o u tp u t en ab le. when t2oe = 1 a nd c/t 2 = 0, the t2 pin will toggle a fter every timer 2 overflow. dcen timer 2 down co u nt en ab le. when timer 2 oper a te s in a u to-relo a d mode a nd exen2 = 1, s etting dcen = 1 will c aus e timer 2 to co u nt u p or down depending on the s t a te of t2ex.
53 3709c?micro?5/11 at89lp51/52 - preliminary 12.2 capture mode in the c a pt u re mode, timer 2 i s a fixed 16- b it timer or co u nter th a t co u nt s u p from min to max. an overflow from max to min s et s b it tf2 in t2con. if exen2 = 1, a 1-to-0 tr a n s ition a t exter- n a l inp u t t2ex a l s o c aus e s the c u rrent v a l u e in th2 a nd tl2 to b e c a pt u red into rcap2h a nd rcap2l, re s pectively. in a ddition, the tr a n s ition a t t2ex c aus e s b it exf2 in t2con to b e s et. the exf2 a nd tf2 b it s c a n gener a te a n interr u pt. c a pt u re mode i s ill us tr a ted in fig u re 12-1 . the timer 2 overflow r a te in c a pt u re mode i s given b y the following eq ua tion: figure 12-1. timer 2 di a gr a m: c a pt u re mode 12.3 auto-reload mode timer 2 c a n b e progr a mmed to co u nt u p or down when config u red in it s 16- b it au to-relo a d mode. thi s fe a t u re i s invoked b y the dcen (down co u nter en ab le) b it loc a ted in the s fr t2mod ( s ee t ab le 12-4 ). upon re s et, the dcen b it i s s et to 0 s o th a t timer 2 will def au lt to co u nt u p. when dcen i s s et, timer 2 c a n co u nt u p or down, depending on the v a l u e of the t2ex pin. a su mm a ry of the a u to-relo a d b eh a vior s i s li s ted in t ab le 12-5 . 12.3.1 up counter fig u re 12-2 s how s timer 2 au tom a tic a lly co u nting u p when dcen = 0. in thi s mode timer 2 co u nt s u p to max a nd then s et s the tf2 b it u pon overflow. the overflow a l s o c aus e s the timer regi s ter s to b e relo a ded with bottom, the 16- b it v a l u e in rcap2h a nd rcap2l. if exen2 = 1, a 16- b it relo a d c a n b e triggered either b y a n overflow or b y a 1-to-0 tr a n s ition a t extern a l inp u t t2ex. thi s tr a n s ition a l s o s et s the exf2 b it. both the tf2 a nd exf2 b it s c a n gener a te a n inter- r u pt. the timer 2 overflow r a te for thi s mode i s given in the following eq ua tion: c a pt u re mode: time-o u t period 65536 s y s tem freq u ency ------------------------------------------------- - tp s 1 + () = tps exf2 t2ex pi n t2 pi n tr2 exen2 c/t2 = 0 c/t2 = 1 capture o verflo w transition detect or timer 2 interr upt rcap2h rcap2l tl2 th2 tf2 osc cdv table 12-5. su mm a ry of a u to-relo a d mode s dcen t2ex direction behavior 0 x up relo a d to bottom 1 0 down u nderflow to max 1 1 up overflow to bottom bottom max u to-relo a d mode: dcen = 0 time-o u t period 65536 rcap2h rcap2l {,} ? s y s tem freq u ency ------------------------------------------------------------------------------ - tp s 1 + () =
54 3709c?micro?5/11 at89lp51/52 - preliminary figure 12-2. timer 2 di a gr a m: a u to-relo a d mode (dcen = 0) figure 12-3. timer 2 w a veform: a u to-relo a d mode (dcen = 0) 12.3.2 up or down counter s etting dcen = 1 en ab le s timer 2 to co u nt u p or down, as s hown in fig u re 12-5 . in thi s mode, the t2ex pin control s the direction of the co u nt (if exen2 = 1). a logic 1 a t t2ex m a ke s timer 2 co u nt u p. when t2cm 1-0 = 00b, the timer will overflow a t max a nd s et the tf2 b it. thi s overflow a l s o c aus e s bottom, the 16- b it v a l u e in rcap2h a nd rcap2l, to b e relo a ded into the timer regi s ter s , th2 a nd tl2, re s pectively. a logic 0 a t t2ex m a ke s timer 2 co u nt down. the timer u nderflow s when th2 a nd tl2 eq ua l bottom, the 16- b it v a l u e s tored in rcap2h a nd rcap2l. the u nderflow s et s the tf2 b it a nd c aus e s max to b e relo a ded into the timer regi s - ter s . the exf2 b it toggle s whenever timer 2 overflow s or u nderflow s a nd c a n b e us ed as a 17th b it of re s ol u tion. in thi s oper a ting mode, exf2 doe s not fl a g a n interr u pt. the b eh a vior of timer 2 when dcen i s en ab led i s s hown in fig u re 12-4 . figure 12-4. timer 2 w a veform: a u to-relo a d mode (dcen = 1) cdv tl2 th2 osc tps max min bottom tf2 s et max min bottom t2ex tf2 s et exf2
55 3709c?micro?5/11 at89lp51/52 - preliminary figure 12-5. timer 2 di a gr a m: a u to-relo a d mode (dcen = 1) the timer overflow/ u nderflow r a te for u p-down co u nting mode i s the sa me as for u p co u nting mode, provided th a t the co u nt direction doe s not ch a nge. ch a nge s to the co u nt direction m a y re su lt in longer or s horter period s b etween time-o u t s . 12.4 baud rate generator timer 2 i s s elected as the bau d r a te gener a tor b y s etting tclk a nd/or rclk in t2con ( t ab le 12-3 ). note th a t the bau d r a te s for tr a n s mit a nd receive c a n b e different if timer 2 i s us ed for the receiver or tr a n s mitter a nd timer 1 i s us ed for the other f u nction. s etting rclk a nd/or tclk p u t s timer 2 into it s bau d r a te gener a tor mode, as s hown in fig u re 12-6 . the bau d r a te gener a tor mode i s s imil a r to the au to-relo a d mode, in th a t a rollover in th2 c aus e s the timer 2 regi s ter s to b e relo a ded with the 16- b it v a l u e in regi s ter s rcap2h a nd rcap2l, which a re pre s et b y s oftw a re. the bau d r a te s in uart mode s 1 a nd 3 a re determined b y timer 2? s overflow r a te a ccording to the following eq ua tion. the timer c a n b e config u red for either timer or co u nter oper a tion. in mo s t a pplic a tion s , it i s con- fig u red for timer oper a tion (cp/t2 = 0). the bau d r a te form u l as a re given b elow. where (rcap2h, rcap2l) i s the content of rcap2h a nd rcap2l t a ken as a 16- b it u n s igned integer. timer 2 as a bau d r a te gener a tor i s s hown in fig u re 12-6 . thi s fig u re i s v a lid only if rclk or tclk = 1 in t2con. note th a t a rollover in th2 doe s not s et tf2 a nd will not gener a te a n inter- r u pt. note too, th a t if exen2 i s s et, a 1-to-0 tr a n s ition in t2ex will s et exf2 bu t will not c aus e a relo a d from (rcap2h, rcap2l) to (th2, tl2). th us when timer 2 i s in us e as a bau d r a te gen- er a tor, t2ex c a n b e us ed as a n extr a extern a l interr u pt. al s o note th a t the b au d r a te a nd freq u ency gener a tor mode s m a y b e us ed s im u lt a neo us ly. tps mode s 1 a nd 3 b au d r a te s timer 2 overflow r a te 16 ----------------------------------------------------------- - = mode s 1, 3 b au d r a te s y s tem freq u ency 16 tp s 1 + () 65536 rcap2h,rcap2l () ? [] ------------------------------------------------------------------------------------------------------------------------------- - - =
56 3709c?micro?5/11 at89lp51/52 - preliminary figure 12-6. timer 2 in b au d r a te gener a tor mode 12.5 frequency generator (p rogrammable clock out) timer 2 c a n gener a te a 50% d u ty cycle clock on t2 (p1.0), as s hown in fig u re 13. . thi s pin, b e s ide s b eing a reg u l a r i/o pin, h as two a ltern a te f u nction s . it c a n b e progr a mmed to inp u t the extern a l clock for timer/co u nter 2 or to toggle it s o u tp u t a t every timer overflow. to config u re the timer/co u nter 2 as a clock gener a tor, b it c/t2 (t2con.1) m us t b e cle a red a nd b it t2oe (t2mod.1) m us t b e s et. bit tr2 (t2con.2) s t a rt s a nd s top s the timer. the clock-o u t freq u ency depend s on the s y s tem freq u ency a nd the relo a d v a l u e of timer 2 c a pt u re regi s ter s (rcap2h, rcap2l), as s hown in the following eq ua tion. in the freq u ency gener a tor mode, timer 2 roll-over s will not gener a te a n interr u pt. thi s b eh a vior i s s imil a r to when timer 2 i s us ed as a bau d-r a te gener a tor. it i s po ss i b le to us e timer 2 as a bau d-r a te gener a tor a nd a clock gener a tor s im u lt a neo us ly. note, however, th a t the bau d-r a te a nd clock-o u t freq u encie s c a nnot b e determined independently from one a nother s ince they b oth us e rcap2h a nd rcap2l. figure 12-7. timer 2 in clock-o u t mode cdv smod1 rclk tclk rx clock tx clock t2ex pi n t2 pi n tr2 "1" "1" "1" "0" "0" "0" timer 1 overflow timer 2 interr upt 2 16 16 rcap2h rcap2l tl2 th2 c/t2 = 0 c/t2 = 1 exf2 transition detect or exen2 osc clock o u t freq u ency s y s tem freq u ency 2 65536 rcap2h,rcap2l () ? [] ------------------------------------------------------------------------------------------- - = osc t2ex pin t2 pin tr2 timer 2 interrupt rcap2h rcap2l tl2 th2 c/t2 exf2 transition detector exen2 cdv 2 t2oe
57 3709c?micro?5/11 at89lp51/52 - preliminary 13. external interrupts the int0 (p3.2) a nd int1 (p3.3) pin s of the at 8 9lp51/52 m a y b e us ed as extern a l interr u pt s o u rce s . the extern a l interr u pt s c a n b e progr a mmed to b e level- a ctiv a ted or tr a n s ition- a ctiv a ted b y s etting or cle a ring b it it1 or it0 in regi s ter tcon. if itx = 0, extern a l interr u pt x i s triggered b y a detected low a t the intx pin. if itx = 1, extern a l interr u pt x i s edge-triggered. in thi s mode if su cce ss ive sa mple s of the intx pin s how a high in one cycle a nd a low in the next cycle, inter- r u pt req u e s t fl a g iex in tcon i s s et. fl a g b it iex then req u e s t s the interr u pt. s ince the extern a l interr u pt pin s a re sa mpled once e a ch clock cycle, a n inp u t high or low s ho u ld hold for a t le as t 2 s y s tem period s to en su re sa mpling. if the extern a l interr u pt i s tr a n s ition- a ctiv a ted, the extern a l s o u rce h as to hold the req u e s t pin high for a t le as t two clock cycle s , a nd then hold it low for a t le as t two clock cycle s to en su re th a t the tr a n s ition i s s een s o th a t interr u pt req u e s t fl a g iex will b e s et. iex will b e au tom a tic a lly cle a red b y the cpu when the s ervice ro u tine i s c a lled if gener- a ted in edge-triggered mode. if the extern a l interr u pt i s level- a ctiv a ted, the extern a l s o u rce h as to hold the req u e s t a ctive u ntil the req u e s ted interr u pt i s a ct ua lly gener a ted. then the extern a l s o u rce m us t de a ctiv a te the req u e s t b efore the interr u pt s ervice ro u tine i s completed, or el s e a nother interr u pt will b e gener a ted. both int0 a nd int1 m a y w a ke u p the device from the power-down s t a te. 14. serial interface (uart) the s eri a l interf a ce on the at 8 9lp51/52 implement s a univer sa l a s ynchrono us receiver/tr a n s mitter (uart). the uart h as the following fe a t u re s : ?f u ll-d u plex oper a tion ? 8 or 9 d a t a bit s ?fr a ming error detection ?m u ltiproce ss or comm u nic a tion mode with a u tom a tic addre ss recognition ?b au d r a te gener a tor u s ing timer 1 or timer 2 ? interr u pt on receive b u ffer f u ll or tr a n s mi ss ion complete ? s ynchrono us s pi or twi m as ter em u l a tion the s eri a l interf a ce i s f u ll-d u plex, which me a n s it c a n tr a n s mit a nd receive s im u lt a neo us ly. it i s a l s o receive- bu ffered, which me a n s it c a n b egin receiving a s econd b yte b efore a previo us ly received b yte h as b een re a d from the receive regi s ter. (however, if the fir s t b yte s till h as not b een re a d when reception of the s econd b yte i s complete, one of the b yte s will b e lo s t.) the s eri a l port receive a nd tr a n s mit regi s ter s a re b oth a cce ss ed a t the s peci a l f u nction regi s ter s buf. writing to s buf lo a d s the tr a n s mit regi s ter, a nd re a ding s buf a cce ss e s a phy s ic a lly s ep a r a te receive regi s ter. the s eri a l port c a n oper a te in the following fo u r mode s . ? mode 0: s eri a l d a t a enter s a nd exit s thro u gh rxd. txd o u tp u t s the s hift clock. eight d a t a b it s a re tr a n s mitted/received, with the l s b fir s t. the bau d r a te i s progr a mm ab le to 1/6 or 1/3 the s y s tem freq u ency in comp a ti b ility mode, 1/4 or 1/2 the s y s tem freq u ency in f as t mode, or v a ri ab le bas ed on time 1. ? mode 1: 10 b it s a re tr a n s mitted (thro u gh txd) or received (thro u gh rxd): a s t a rt b it (0), 8 d a t a b it s (l s b fir s t), a nd a s top b it (1). on receive, the s top b it goe s into rb 8 in the s peci a l f u nction regi s ter s con. the bau d r a te i s v a ri ab le bas ed on timer 1 or timer 2. ? mode 2: 11 b it s a re tr a n s mitted (thro u gh txd) or received (thro u gh rxd): a s t a rt b it (0), 8 d a t a b it s (l s b fir s t), a progr a mm ab le 9th d a t a b it, a nd a s top b it (1). on tr a n s mit, the 9th d a t a b it (tb 8 in s con) c a n b e ass igned the v a l u e of ?0? or ?1?. for ex a mple, the p a rity b it (p, in the p s w) c a n b e moved into tb 8 . on receive, the 9th d a t a b it goe s into rb 8 in the
58 3709c?micro?5/11 at89lp51/52 - preliminary s peci a l f u nction regi s ter s con, while the s top b it i s ignored. the bau d r a te i s progr a mm ab le to either 1/16 or 1/32 the s y s tem freq u ency. ? mode 3: 11 b it s a re tr a n s mitted (thro u gh txd) or received (thro u gh rxd): a s t a rt b it (0), 8 d a t a b it s (l s b fir s t), a progr a mm ab le 9th d a t a b it, a nd a s top b it (1). in f a ct, mode 3 i s the sa me as mode 2 in a ll re s pect s except the bau d r a te, which i s v a ri ab le bas ed on timer 1 or timer 2 in mode 3. in a ll fo u r mode s , tr a n s mi ss ion i s initi a ted b y a ny in s tr u ction th a t us e s s buf as a de s tin a tion regi s ter. reception i s initi a ted in mode 0 b y the condition ri = 0 a nd ren = 1. reception i s initi- a ted in the other mode s b y the incoming s t a rt b it if ren = 1. note s :1. s mod0 i s loc a ted a t pcon.6. 2. f s y s = s y s tem freq u ency. the bau d r a te depend s on s mod1 (pcon.7). table 14-1. s con ? s eri a l port control regi s ter s con addre ss = 9 8 h re s et v a l u e = 0000 0000b bit addre ssab le s m0/fe s m1 s m2 ren tb 8 rb 8 t1 ri bit7 6543210 ( s mod0 = 0/1) (1) symbol function fe fr a ming error b it. thi s b it i s s et b y the receiver when a n inv a lid s top b it i s detected. the fe b it i s not cle a red b y v a lid fr a me s a nd m us t b e cle a red b y s oftw a re. the s mod0 b it m us t b e s et to en ab le a cce ss to the fe b it. fe will b e s et reg a rdle ss of the s t a te of s mod0. s m0 s eri a l port mode bit 0, ( s mod0 m us t = 0 to a cce ss b it s m0) s m1 s eri a l port mode bit 1 s m2 en ab le s the a u tom a tic addre ss recognition fe a t u re in mode s 2 or 3. if s m2 = 1 then rl will not b e s et u nle ss the received 9th d a t a b it (rb 8 ) i s 1, indic a ting a n a ddre ss , a nd the received b yte i s a given or bro a dc as t addre ss . in mode 1, if s m2 = 1 then rl will not b e a ctiv a ted u nle ss a v a lid s top b it w as received, a nd the received b yte i s a given or bro a dc as t addre ss . in mode 0, s m2 determine s the idle s t a te of the s hift clock su ch th a t the clock i s the inver s e of s m2, i.e. when s m2 = 0 the clock idle s high a nd when s m2 = 1 the clock idle s low. ren en ab le s s eri a l reception. s et b y s oftw a re to en ab le reception. cle a r b y s oftw a re to di sab le reception. tb 8 the 9th d a t a b it th a t will b e tr a n s mitted in mode s 2 a nd 3. s et or cle a r b y s oftw a re as de s ired. in mode 0, s etting tb 8 en ab le s timer 1 as the s hift clock gener a tor. rb 8 in mode s 2 a nd 3, the 9th d a t a b it th a t w as received. in mode 1, if s m2 = 0, rb 8 i s the s top b it th a t w as received. in mode 0, rb 8 i s not us ed. ti tr a n s mit interr u pt fl a g. s et b y h a rdw a re a t the end of the 8 th b it time in mode 0, or a t the b eginning of the s top b it in the other mode s , in a ny s eri a l tr a n s mi ss ion. m us t b e cle a red b y s oftw a re. ri receive interr u pt fl a g. s et b y h a rdw a re a t the end of the 8 th b it time in mode 0, or h a lfw a y thro u gh the s top b it time in the other mode s , in a ny s eri a l reception (except s ee s m2). m us t b e cle a red b y s oftw a re. sm0 sm1 mode description baud rate (compat.) (2) baud rate (fast) (2) 000 s hift regi s ter f s y s /3 or f s y s /6 or timer 1 f s y s /2 or f s y s /4 or timer 1 011 8 - b it uart v a ri ab le (timer 1 or timer 2) v a ri ab le (timer 1 or timer 2) 1029- b it uart f s y s /32 or f s y s /16 f s y s /32 or f s y s /16 1139- b it uart v a ri ab le (timer 1 or timer 2) v a ri ab le (timer 1 or timer 2)
59 3709c?micro?5/11 at89lp51/52 - preliminary 14.1 multiprocessor communications mode s 2 a nd 3 h a ve a s peci a l provi s ion for m u ltiproce ss or comm u nic a tion s . in the s e mode s , 9d a t a b it s a re received, followed b y a s top b it. the 9th b it goe s into rb 8 . then come s a s top b it. the port c a n b e progr a mmed su ch th a t when the s top b it i s received, the s eri a l port interr u pt i s a ctiv a ted only if rb 8 = 1. thi s fe a t u re i s en ab led b y s etting b it s m2 in s con. the following ex a mple s how s how to us e the s eri a l interr u pt for m u ltiproce ss or comm u nic a tion s . when the m as ter proce ss or m us t tr a n s mit a b lock of d a t a to one of s ever a l s l a ve s , it fir s t s end s o u t a n a ddre ss b yte th a t identifie s the t a rget s l a ve. an a ddre ss b yte differ s from a d a t a b yte in th a t the 9th b it i s ?1? in a n a ddre ss b yte a nd ?0? in a d a t a b yte. with s m2 = 1, no s l a ve i s interr u pted b y a d a t a b yte. an a ddre ss b yte, however, interr u pt s a ll s l a ve s . e a ch s l a ve c a n ex a mine the received b yte a nd s ee if it i s b eing a ddre ss ed. the a ddre ss ed s l a ve cle a r s it s s m2 b it a nd prep a re s to receive the d a t a b yte s th a t follow s . the s l a ve s th a t a re not a ddre ss ed s et their s m2 b it s a nd ignore the d a t a b yte s . s ee ?a u tom a tic addre ss recognition? on p a ge 61. the s m2 b it c a n b e us ed to check the v a lidity of the s top b it in mode 1. in a mode 1 reception, if s m2 = 1, the receive interr u pt i s not a ctiv a ted u nle ss a v a lid s top b it i s received. 14.2 baud rates the bau d r a te in mode 0 depend s on the v a l u e of the s mod1 b it in s peci a l f u nction regi s ter pcon.7. if s mod1 = 0 (the v a l u e on re s et) a nd tb 8 =0, the bau d r a te i s 1/4 of the s y s tem fre- q u ency in f as t mode. if s mod1 = 1 a nd tb 8 = 0, the bau d r a te i s 1/2 of the s y s tem freq u ency, as s hown in the following eq ua tion: :in comp a ti b ility mode the bau d r a te i s 1/6 of the s y s tem freq u ency, s c a ling to 1/3 when s mod1 = 1. the bau d r a te in mode 2 a l s o depend s on the v a l u e of the s mod1 b it. if s mod1 = 0, the bau d r a te i s 1/32 of the s y s tem freq u ency. if s mod1 = 1, the bau d r a te i s 1/16 of the s y s tem fre- q u ency, as s hown in the following eq ua tion: 14.2.1 using timer 1 to generate baud rates s etting tb 8 = 1 in mode 0 en ab le s timer 1 as the bau d r a te gener a tor. when timer 1 i s the bau d r a te gener a tor for mode 0, the bau d r a te s a re determined b y the timer 1 overflow r a te a nd the v a l u e of s mod1 a ccording to the following eq ua tion: mode 0 b au d r a te tb 8 = 0 2 s mod1 4 -------------------- s y s tem freq u ency = mode 0 b au d r a te tb 8 = 0 2 s mod1 6 -------------------- s y s tem freq u ency = mode 2 b au d r a te 2 s mod1 32 -------------------- s y s tem freq u ency = mode 0 b au d r a te tb 8 = 1 2 s mod1 4 -------------------- (timer 1 overflow r a te) =
60 3709c?micro?5/11 at89lp51/52 - preliminary the timer 1 overflow r a te norm a lly determine s the bau d r a te s in mode s 1 a nd 3. when timer 1 i s the bau d r a te gener a tor, the bau d r a te s a re determined b y the timer 1 overflow r a te a nd the v a l u e of s mod1 a ccording to the following eq ua tion: the timer 1 interr u pt s ho u ld b e di sab led in thi s a pplic a tion. the timer it s elf c a n b e config u red for either timer or co u nter oper a tion in a ny of it s 3 r u nning mode s . in the mo s t typic a l a pplic a - tion s , it i s config u red for timer oper a tion in au to-relo a d mode (high ni bb le of tmod = 0010b). in thi s c as e, the bau d r a te i s given b y the following form u l a : t ab le 14-2 li s t s commonly us ed bau d r a te s a nd how they c a n b e o b t a ined from timer 1. 14.2.2 using timer 2 to generate baud rates timer 2 i s s elected as the bau d r a te gener a tor b y s etting tclk a nd/or rclk in t2con. under the s e condition s , the bau d r a te s for tr a n s mit a nd receive c a n b e s im u lt a neo us ly different b y us ing timer 1 for tr a n s mit a nd timer 2 for receive, or vice ver sa . the bau d r a te gener a tor mode mode s 1, 3 b au d r a te 2 s mod1 32 -------------------- (timer 1 overflow r a te) = mode s 1, 3 b au d r a te 2 s mod1 32 -------------------- s y s tem freq u ency 256 th1 () ? [] ------------------------------------------------- - 1 tp s 1 + -------------------- - = table 14-2. commonly u s ed b au d r a te s gener a ted b y timer 1 baud rate f osc (mhz) cdv smod1 timer 1 c/t mode tps reload value mode 0 m a x: 6 mhz 12 0 1 x x 0 x mode 2 m a x: 750k 12 0 1 x x 0 x mode s 1, 3 m a x: 750k 12 0 1 0 2 0 f4h 19.2k 11.059 0 1 0 2 0 dch 9.6k 11.059 0 0 0 2 0 dch 4. 8 k 11.05900020 b 8 h 2.4k 11.059 0 0 0 2 0 70h 1.2k 11.059 0 0 0 1 0 fee0h 137.5 11.9 8 600010f55ch 110 6 0 1 0 1 0 f2afh 110 1200010f2afh 19.2k 11.059 1 1 0 2 5 fdh 9.6k 11.059 1 0 0 2 5 fdh 4. 8 k 11.05910025 fah 2.4k 11.059 1 0 0 2 5 f4h 1.2k 11.059 1 0 0 2 5 e 8 h 137.5 11.9 8 610025 1dh 110 6 1 0 0 2 5 72h 110 12 1 0 0 1 5 feebh
61 3709c?micro?5/11 at89lp51/52 - preliminary i s s imil a r to the au to-relo a d mode, in th a t a rollover c aus e s the timer 2 regi s ter s to b e relo a ded with the 16- b it v a l u e in regi s ter s rcap2h a nd rcap2l, which a re pre s et b y s oftw a re. in thi s c as e, the bau d r a te s in mode s 1 a nd 3 a re determined b y timer 2? s overflow r a te a ccording to the following eq ua tion: t ab le 14-3 li s t s commonly us ed bau d r a te s a nd how they c a n b e o b t a ined from timer 2. 14.3 framing error detection in a ddition to a ll of it s usua l mode s , the uart c a n perform fr a ming error detection b y looking for mi ss ing s top b it s , a nd au tom a tic a ddre ss recognition. when us ed for fr a ming error detect, the uart look s for mi ss ing s top b it s in the comm u nic a tion. a mi ss ing b it will s et the fe b it in the s con regi s ter. the fe b it s h a re s the s con.7 b it with s m0 a nd the f u nction of s con.7 i s deter- mined b y pcon.6 ( s mod0). if s mod0 i s s et then s con.7 f u nction s as fe. s con.7 f u nction s as s m0 when s mod0 i s cle a red. when us ed as fe, s con.7 c a n only b e cle a red b y s oftw a re. the fe b it will b e s et b y a fr a ming error reg a rdle ss of the s t a te of s mod0. 14.4 automatic ad dress recognition a u tom a tic addre ss recognition i s a fe a t u re which a llow s the uart to recognize cert a in a ddre ss e s in the s eri a l b it s tre a m b y us ing h a rdw a re to m a ke the comp a ri s on s . thi s fe a t u re sa ve s a gre a t de a l of s oftw a re overhe a d b y elimin a ting the need for the s oftw a re to ex a mine every s eri a l a ddre ss which p ass e s b y the s eri a l port. thi s fe a t u re i s en ab led b y s etting the s m2 b it in s con for mode s 1, 2 or 3. in the 9- b it uart mode s , mode 2 a nd mode 3, the receive table 14-3. commonly u s ed b au d r a te s gener a ted b y timer 2 baud rate f osc (mhz) cdv timer 2 cp/rl2 c/t2 tclk or rclk reload value m a x: 750k 12 0 0 0 1 ffffh 19.2k 11.059 0 0 0 1 ffdch 9.6k 11.059 0 0 0 1 ffb 8 h 4. 8 k 11.059 0 0 0 1 ff70h 2.4k 11.059 0 0 0 1 fee0h 1.2k 11.059 0 0 0 1 fdc0h 137.5 11.9 8 60 0 0 1 eab 8 h 110 6 0 0 0 1 f2afh 110 12 0 0 0 1 e55eh 19.2k 11.059 1 0 0 1 ffeeh 9.6k 11.059 1 0 0 1 ffdch 4. 8 k 11.059 1 0 0 1 ffb 8 h 2.4k 11.059 1 0 0 1 ff70h 1.2k 11.059 1 0 0 1 fee0h 137.5 11.9 8 6 1 0 0 1 f55ch 110 12 1 0 0 1 f2afh mode s 1 a nd 3 b au d r a te 1 16 ------ s y s tem freq u ency 65536 rcap2h,rcap2l () ? [] --------------------------------------------------------------------------------- =
62 3709c?micro?5/11 at89lp51/52 - preliminary interr u pt fl a g (ri) will b e au tom a tic a lly s et when the received b yte cont a in s either the ?given? a ddre ss or the ?bro a dc as t? a ddre ss . the 9- b it mode req u ire s th a t the 9th inform a tion b it b e a ?1? to indic a te th a t the received inform a tion i s a n a ddre ss a nd not d a t a . in mode 1 ( 8 - b it) the ri fl a g will b e s et if s m2 i s en ab led a nd the inform a tion received h as a v a lid s top b it following the 8 th a ddre ss b it s a nd the inform a tion i s either a given or bro a dc as t a ddre ss . a u tom a tic addre ss recognition i s not a v a il ab le d u ring mode 0. u s ing the a u tom a tic addre ss recognition fe a t u re a llow s a m as ter to s electively comm u nic a te with one or more s l a ve s b y invoking the given s l a ve a ddre ss or a ddre ss e s . all of the s l a ve s m a y b e cont a cted b y us ing the bro a dc as t a ddre ss . two s peci a l f u nction regi s ter s a re us ed to define the s l a ve? s a ddre ss , s addr, a nd the a ddre ss m as k, s aden. s aden i s us ed to define which b it s in the s addr a re to b e us ed a nd which b it s a re ?don?t c a re?. the s aden m as k c a n b e logic a lly anded with the s addr to cre a te the ?given? a ddre ss which the m as ter will us e for a ddre ss ing e a ch of the s l a ve s . u s e of the given a ddre ss a llow s m u ltiple s l a ve s to b e recognized while excl u ding other s . the following ex a mple s s how the ver sa tility of thi s s cheme: s l a ve 0 s addr = 1100 0000 s aden = 1111 1101 given = 1100 00x0 s l a ve 1 s addr = 1100 0000 s aden = 1111 1110 given = 1100 000x in the previo us ex a mple, s addr i s the sa me a nd the s aden d a t a i s us ed to differenti a te b etween the two s l a ve s . s l a ve 0 req u ire s a ?0? in b it 0 a nd it ignore s b it 1. s l a ve 1 req u ire s a ?0? in b it 1 a nd b it 0 i s ignored. a u niq u e a ddre ss for s l a ve 0 wo u ld b e 1100 0010 s ince s l a ve 1 req u ire s a ?0? in b it 1. a u niq u e a ddre ss for s l a ve 1 wo u ld b e 1100 0001 s ince a ?1? in b it 0 will excl u de s l a ve 0. both s l a ve s c a n b e s elected a t the sa me time b y a n a ddre ss which h as b it 0 = 0 (for s l a ve 0) a nd b it 1 = 0 (for s l a ve 1). th us , b oth co u ld b e a ddre ss ed with 1100 0000. in a more complex s y s tem, the following co u ld b e us ed to s elect s l a ve s 1 a nd 2 while excl u ding s l a ve 0: s l a ve 0 s addr = 1100 0000 s aden = 1111 1001 given = 1100 0xx0 s l a ve 1 s addr = 1110 0000 s aden = 1111 1010 given = 1110 0x0x s l a ve 2 s addr = 1110 0000 s aden = 1111 1100 given = 1110 00xx in the ab ove ex a mple, the differenti a tion a mong the 3 s l a ve s i s in the lower 3 a ddre ss b it s . s l a ve 0 req u ire s th a t b it 0 = 0 a nd it c a n b e u niq u ely a ddre ss ed b y 1110 0110. s l a ve 1 req u ire s th a t b it 1 = 0 a nd it c a n b e u niq u ely a ddre ss ed b y 1110 a nd 0101. s l a ve 2 req u ire s th a t b it 2 = 0 a nd it s u niq u e a ddre ss i s 1110 0011. to s elect s l a ve s 0 a nd 1 a nd excl u de s l a ve 2, us e a ddre ss 1110 0100, s ince it i s nece ssa ry to m a ke b it 2 = 1 to excl u de s l a ve 2.
63 3709c?micro?5/11 at89lp51/52 - preliminary the bro a dc as t addre ss for e a ch s l a ve i s cre a ted b y t a king the logic or of s addr a nd s aden. zero s in thi s re su lt a re trended as don?t c a re s . in mo s t c as e s , interpreting the don?t c a re s as one s , the b ro a dc as t a ddre ss will b e ff hex a decim a l. upon re s et s addr ( s fr a ddre ss 0a9h) a nd s aden ( s fr a ddre ss 0b9h) a re lo a ded with ?0? s . thi s prod u ce s a given a ddre ss of a ll ?don?t c a re s ? as well as a bro a dc as t a ddre ss of a ll ?don?t c a re s ?. thi s effectively di sab le s the a u tom a tic addre ss ing mode a nd a llow s the microcon- troller to us e s t a nd a rd 8 0c51-type uart driver s which do not m a ke us e of thi s fe a t u re. 14.5 more about mode 0 in mode 0, the uart i s config u red as either a two wire h a lf-d u plex or three wire f u ll-d u plex s yn- chrono us s eri a l interf a ce. in two-wire mode s eri a l d a t a enter s a nd exit s thro u gh rxd a nd txd o u tp u t s the s hift clock. in three-wire mode s eri a l d a t a enter s thro u gh mi s o, exit s thro u gh mo s i a nd s ck o u tp u t s the s hift clock. eight d a t a b it s a re tr a n s mitted/received, with the l s b fir s t. fig- u re 14-3 a nd fig u re 14-5 on p a ge 67 s how s implified f u nction a l di a gr a m s of the s eri a l port in mode 0 a nd ass oci a ted timing. the bau d r a te i s progr a mm ab le to 1/2 or 1/4 the s y s tem fre- q u ency b y s etting/cle a ring the s mod1 b it in f as t mode, or 1/3 or 1/6 the s y s tem freq u ency in comp a ti b ility mode. however, ch a nging s mod1 h as a n effect on the rel a tion s hip b etween the clock a nd d a t a as de s cri b ed b elow. the bau d r a te c a n a l s o b e gener a ted b y timer 1 b y s etting tb 8 . t ab le 14-4 li s t s the bau d r a te option s for mode 0. 14.5.1 two-wire (half-duplex) mode tr a n s mi ss ion i s initi a ted b y a ny in s tr u ction th a t us e s s buf as a de s tin a tion regi s ter. the ?write to s buf? s ign a l a l s o lo a d s a ?1? into the 9th po s ition of the tr a n s mit s hift regi s ter a nd tell s the tx control block to b egin a tr a n s mi ss ion. the intern a l timing i s su ch th a t one f u ll b it s lot m a y el a p s e b etween ?write to s buf? a nd a ctiv a tion of s end. s end tr a n s fer s the o u tp u t of the s hift regi s ter to the a ltern a te o u tp u t f u nction line of p3.0, a nd a l s o tr a n s fer s s hift clock to the a ltern a te o u tp u t f u nction line of p3.1. a s d a t a b it s s hift o u t to the right, ?0? s come in from the left. when the m s b of the d a t a b yte i s a t the o u tp u t po s ition of the s hift regi s ter, the ?1? th a t w as initi a lly lo a ded into the 9th po s ition i s j us t to the left of the m s b, a nd a ll po s ition s to the left of th a t cont a in ?0? s . thi s condition fl a g s the tx control b lock to do one l as t s hift, then de a ctiv a te s end a nd s et ti. reception i s initi a ted b y the condition ren = 1 a nd ri = 0. at the next clock cycle, the rx con- trol u nit write s the b it s 11111110b to the receive s hift regi s ter a nd a ctiv a te s receive in the next clock ph as e. receive en ab le s s hift clock to the a ltern a te o u tp u t f u nction line of p3.1. a s d a t a b it s come in from the right, ?1? s s hift o u t to the left. when the ?0? th a t w as initi a lly lo a ded into the right-mo s t po s ition a rrive s a t the left-mo s t po s ition in the s hift regi s ter, it fl a g s the rx control b lock to do one l as t s hift a nd lo a d s buf. then receive i s cle a red a nd ri i s s et. the rel a tion s hip b etween the s hift clock a nd d a t a i s determined b y the com b in a tion of the s m2 a nd s mod1 b it s as li s ted in t ab le 14-5 a nd s hown in fig u re . the s m2 b it determine s the idle table 14-4. mode 0 b au d r a te s tb8 smod1 baud rate (fast) baud rate (compatibility) 00 f s y s /4 f s y s /6 01 f s y s /2 f s y s /3 1 0 (timer 1 overflow) / 4 (timer 1 overflow) / 4 1 1 (timer 1 overflow) / 2 (timer 1 overflow) / 2
64 3709c?micro?5/11 at89lp51/52 - preliminary s t a te of the clock when not c u rrently tr a n s mitting/receiving. the s mod1 b it determine s if the o u tp u t d a t a i s s t ab le for b oth edge s of the clock, or j us t one. in two-wire config u r a tion mode 0 m a y b e us ed as a h a rdw a re a cceler a tor for s oftw a re em u l a - tion of s eri a l interf a ce s su ch as a h a lf-d u plex s eri a l peripher a l interf a ce ( s pi) m as ter in mode (0,0) or (1,1) or a two-wire interf a ce (twi) in m as ter mode. an ex a mple of mode 0 em u l a ting a twi m as ter device i s s hown in fig u re 14-2 . in thi s ex a mple, the s t a rt, s top, a nd a cknowledge a re h a ndled in s oftw a re while the b yte tr a n s mi ss ion i s done in h a rdw a re. f a lling/ri s ing edge s on txd a re cre a ted b y s etting/cle a ring s m2. ri s ing/f a lling edge s on rxd a re forced b y s et- ting/cle a ring the p3.0 regi s ter b it. s m2 a nd p3.0 m us t b e 1 while the b yte i s b eing tr a n s ferred. figure 14-1. mode 0 w a veform s (two-wire) figure 14-2. uart mode 0 twi em u l a tion ( s mod1 = 1) table 14-5. mode 0 clock a nd d a t a mode s sm2 smod1 clock idle data changes data sampled 0 0 high while clock i s high po s itive edge of clock 0 1 high neg a tive edge of clock po s itive edge of clock 1 0 low while clock i s low neg a tive edge of clock 1 1 low neg a tive edge of clock po s itive edge of clock 7 rxd (tx) txd 6 5 4 3 2 1 0 rxd (rx) 01234567 7 rxd (tx) txd 6 5 4 3 2 1 0 rxd (rx) 01234567 7 rxd (tx) txd 6 5 4 3 2 1 0 rxd (rx) 01234567 7 rxd (tx) txd 6 5 4 3 2 1 0 rxd (rx) 01234567 s mod1 = 0 s m2 = 0 s mod1 = 1 s m2 = 0 s mod1 = 0 s m2 = 1 s mod1 = 1 s m2 = 1 7 ( s da) rxd ( s cl) txd 6 5 4 3 2 1 0 ack s m2 p3.0 write to s buf ti sa mple ack
65 3709c?micro?5/11 at89lp51/52 - preliminary figure 14-3. s eri a l port mode 0 (two-wire) internal b u s f s y s internal b u s txd ( s hift clock) rxd ( d a t a out ) txd ( s hift clock) rxd ( d a t a in ) write t o s b u f s end s hift ti write t o s con (clear ri ) s hift receive ri ?1? 2 tb 8 0 1 timer 1 o verf l o w 2 s mod1 0 1 s m2
66 3709c?micro?5/11 at89lp51/52 - preliminary mode 0 tr a n s fer s d a t a l s b fir s t where as s pi or twi a re gener a lly m s b fir s t. em u l a tion of the s e interf a ce s m a y req u ire b it rever sa l of the tr a n s ferred d a t a b yte s . the following code ex a mple rever s e s the b it s in the a cc u m u l a tor: ex: mov r7, #8 revrs: rlc a ; c << msb (acc) xch a, r6 rrc a ; msb (acc) >> b xch a, r6 djnz r7, revrs 14.5.2 three-wire (full-duplex) mode three-wire mode i s s imil a r to two-wire except th a t the s hift d a t a inp u t a nd d a t a o u tp u t a re s ep- a r a ted for f u ll-d u plex oper a tion. three-wire mode i s en ab led b y s etting the s pen b it in tconb. tr a n s mi ss ion i s initi a ted b y a ny in s tr u ction th a t us e s s buf as a de s tin a tion regi s ter. the ?write to s buf? s ign a l a l s o lo a d s a ?1? into the 9th po s ition of the tr a n s mit s hift regi s ter a nd tell s the tx control block to b egin a tr a n s mi ss ion. the intern a l timing i s su ch th a t one f u ll b it s lot m a y el a p s e b etween ?write to s buf? a nd a ctiv a tion of s end. s end tr a n s fer s the o u tp u t of the s hift regi s ter to the a ltern a te o u tp u t f u nction line of p1.5, a nd a l s o tr a n s fer s s hift clock to the a ltern a te o u tp u t f u nction line of p1.7. a s d a t a b it s s hift o u t to the right, ?0? s come in from the left. when the m s b of the d a t a b yte i s a t the o u tp u t po s ition of the s hift regi s ter, the ?1? th a t w as initi a lly lo a ded into the 9th po s ition i s j us t to the left of the m s b, a nd a ll po s ition s to the left of th a t cont a in ?0? s . thi s condition fl a g s the tx control b lock to do one l as t s hift, then de a ctiv a te s end a nd s et ti. reception occ u r s s im u lt a neo us ly with tr a n s mi ss ion if ren = 1. d a t a i s inp u t from p1.6. when ren = 1 a ny write to s buf c aus e s the rx control u nit to write the b it s 11111110b to the receive s hift regi s ter a nd a ctiv a te s receive in the next clock ph as e. a s d a t a b it s come in from the right, ?1? s s hift o u t to the left. when the ?0? th a t w as initi a lly lo a ded into the right-mo s t po s i- tion a rrive s a t the left-mo s t po s ition in the s hift regi s ter, it fl a g s the rx control b lock to do one l as t s hift a nd lo a d s buf. then receive i s cle a red a nd ri i s s et. when ren = 0, the receiver i s not en ab led. when a tr a n s mi ss ion occ u r s , s buf will not b e u pd a ted a nd ri will not b e s et even tho u gh s eri a l d a t a i s received on p1.6. the rel a tion s hip b etween the s hift clock a nd d a t a i s identic a l to two-wire mode as li s ted in t ab le 14-5 a nd s hown in fig u re . three-wire mode us e s different i/o s from two-wire mode a nd c a n b e connected to s pi s l a ve device s as s hownin fig u re 14-4 . it i s po ss i b le to time s h a re the uart h a rdw a re b etween s pi device s connected on p1 a nd uart device s on p3 with the c a ve a t th a t a ny as ynchrono us reception s on the rxd pin will b e ignored while the uart i s in mode 0. figure 14-4. s pi connection s for uart mode 0 8-bit shift register master slave msb lsb msb lsb 8-bit shift register miso miso mosi mosi ss gpio sck sck clock generator at89lp52
67 3709c?micro?5/11 at89lp51/52 - preliminary figure 14-5. s eri a l port mode 0 (three-wire) internal bu s f s y s internal b u s s ck ( s hift clock) mo s i mi s o write t o s b u f s end s hift ti ?1? 2 tb 8 0 1 timer 1 o verf l o w 2 s mod1 0 1 s m2 mo s i p1.5 alt output function s ck p1.7 alt output function mi s o p1.6 alt output function s erial port interrupt ti (data out) (data in) ri
68 3709c?micro?5/11 at89lp51/52 - preliminary 14.6 more about mode 1 ten b it s a re tr a n s mitted (thro u gh txd), or received (thro u gh rxd): a s t a rt b it (0), 8 d a t a b it s (l s b fir s t), a nd a s top b it (1). on receive, the s top b it goe s into rb 8 in s con. in the at 8 9lp51/52, the bau d r a te i s determined either b y the timer 1 overflow r a te, the timer 2 over- flow r a te, or b oth. in thi s c as e one timer i s for tr a n s mit a nd the other i s for receive. fig u re 14-6 s how s a s implified f u nction a l di a gr a m of the s eri a l port in mode 1 a nd ass oci a ted timing s for tr a n s mit a nd receive. tr a n s mi ss ion i s initi a ted b y a ny in s tr u ction th a t us e s s buf as a de s tin a tion regi s ter. the ?write to s buf? s ign a l a l s o lo a d s a ?1? into the 9th b it po s ition of the tr a n s mit s hift regi s ter a nd fl a g s the tx control u nit th a t a tr a n s mi ss ion i s req u e s ted. tr a n s mi ss ion a ct ua lly commence s a t s 1p1 of the m a chine cycle following the next rollover in the divide- b y-16 co u nter. th us , the b it time s a re s ynchronized to the divide- b y-16 co u nter, not to the ?write to s buf? s ign a l. the tr a n s mi ss ion b egin s when s end i s a ctiv a ted, which p u t s the s t a rt b it a t txd. one b it time l a ter, data i s a ctiv a ted, which en ab le s the o u tp u t b it of the tr a n s mit s hift regi s ter to txd. the fir s t s hift p u l s e occ u r s one b it time a fter th a t. a s d a t a b it s s hift o u t to the right, ?0? s a re clocked in from the left. when the m s b of the d a t a b yte i s a t the o u tp u t po s ition of the s hift regi s ter, the ?1? th a t w as initi a lly lo a ded into the 9th po s ition i s j us t to the left of the m s b, a nd a ll po s ition s to the left of th a t cont a in ?0? s . thi s condition fl a g s the tx control u nit to do one l as t s hift, then de a ctiv a te s end a nd s et ti. thi s occ u r s a t the tenth divide- b y-16 rollover a fter ?write to s buf.? reception i s initi a ted b y a 1-to-0 tr a n s ition detected a t rxd. for thi s p u rpo s e, rxd i s sa mpled a t a r a te of 16 time s the e s t ab li s hed bau d r a te. when a tr a n s ition i s detected, the divide- b y-16 co u nter i s immedi a tely re s et, a nd 1ffh i s written into the inp u t s hift regi s ter. re s etting the divide- b y-16 co u nter a lign s it s roll-over s with the b o u nd a rie s of the incoming b it time s . the 16 s t a te s of the co u nter divide e a ch b it time into 16th s . at the 7th, 8 th, a nd 9th co u nter s t a te s of e a ch b it time, the b it detector sa mple s the v a l u e of rxd. the v a l u e a ccepted i s the v a l u e th a t w as s een in a t le as t 2 of the 3 sa mple s . thi s i s done to reject noi s e. in order to reject f a l s e b it s , if the v a l u e a ccepted d u ring the fir s t b it time i s not 0, the receive circ u it s a re re s et a nd the u nit contin u e s looking for a nother 1-to-0 tr a n s ition. if the s t a rt b it i s v a lid, it i s s hifted into the inp u t s hift regi s ter, a nd reception of the re s t of the fr a me proceed s . a s d a t a b it s come in from the right, ?1? s s hift o u t to the left. when the s t a rt b it a rrive s a t the left- mo s t po s ition in the s hift regi s ter, (which i s a 9- b it regi s ter in mode 1), it fl a g s the rx control b lock to do one l as t s hift, lo a d s buf a nd rb 8 , a nd s et ri. the s ign a l to lo a d s buf a nd rb 8 a nd to s et ri i s gener a ted if, a nd only if, the fo llowing condition s a re met a t the time the fin a l s hift p u l s e i s gener a ted. ri = 0 a nd either s m2 = 0, or the received s top b it = 1 if either of the s e two condition s i s not met, the received fr a me i s irretriev ab ly lo s t. if b oth condi- tion s a re met, the s top b it goe s into rb 8 , the 8 d a t a b it s go into s buf, a nd ri i s a ctiv a ted. at thi s time, whether or not the ab ove condition s a re met, the u nit contin u e s looking for a 1-to-0 tr a n s ition in rxd.
69 3709c?micro?5/11 at89lp51/52 - preliminary figure 14-6. s eri a l port mode 1 tx clock write to s buf internal bu s read s buf load s buf s buf s hift input s hift reg. (9 bit s ) bit detector 1-to-0 tran s ition detector s erial port interrupt write to s buf 2 s mod1 ?0? ?1? timer 1 overflow rxd rx clock rx clock rx control s tart s tart data s end s ample 16 16 tx control ti t i zero detector s buf txd internal bu s ?1? d q cl s load s buf s hift s hift 1ffh ri s end data s hift txd ti d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 s top bit tran s mit s tart bit 16 re s et s tart bit s top bit rx clock bit detector s ample time s s hift receive rxd ri timer 2 overflow tclk rclk ?0? ?0? ?1? ?1?
70 3709c?micro?5/11 at89lp51/52 - preliminary 14.7 more about modes 2 and 3 eleven b it s a re tr a n s mitted (thro u gh txd), or received (thro u gh rxd): a s t a rt b it (0), 8 d a t a b it s (l s b fir s t), a progr a mm ab le 9th d a t a b it, a nd a s top b it (1). on tr a n s mit, the 9th d a t a b it (tb 8 ) c a n b e ass igned the v a l u e of ?0? or ?1?. on receive, the 9th d a t a b it goe s into rb 8 in s con. the bau d r a te i s progr a mm ab le to either 1/16 or 1/32 of the o s cill a tor freq u ency in mode 2. mode 3 m a y h a ve a v a ri ab le bau d r a te gener a ted from either timer 1 or timer 2, depending on the s t a te of rclk a nd tclk. fig u re s 14-7 a nd 14- 8 s how a f u nction a l di a gr a m of the s eri a l port in mode s 2 a nd 3. the receive portion i s ex a ctly the sa me as in mode 1. the tr a n s mit portion differ s from mode 1 only in the 9th b it of the tr a n s mit s hift regi s ter. tr a n s mi ss ion i s initi a ted b y a ny in s tr u ction th a t us e s s buf as a de s tin a tion regi s ter. the ?write to s buf? s ign a l a l s o lo a d s tb 8 into the 9th b it po s ition of the tr a n s mit s hift regi s ter a nd fl a g s the tx control u nit th a t a tr a n s mi ss ion i s req u e s ted. tr a n s mi ss ion commence s a t s 1p1 of the m a chine cycle following the next rollover in the divide- b y-16 co u nter. th us , the b it time s a re s yn- chronized to the divide- b y-16 co u nter, not to the ?write to s buf? s ign a l. the tr a n s mi ss ion b egin s when s end i s a ctiv a ted, which p u t s the s t a rt b it a t txd. one b it time l a ter, data i s a ctiv a ted, which en ab le s the o u tp u t b it of the tr a n s mit s hift regi s ter to txd. the fir s t s hift p u l s e occ u r s one b it time a fter th a t. the fir s t s hift clock s a ?1? (the s top b it) into the 9th b it po s ition of the s hift regi s ter. there a fter, only ?0? s a re clocked in. th us , as d a t a b it s s hift o u t to the right, ?0? s a re clocked in from the left. when tb 8 i s a t the o u tp u t po s ition of the s hift regi s ter, then the s top b it i s j us t to the left of tb 8 , a nd a ll po s ition s to the left of th a t cont a in ?0? s . thi s con- dition fl a g s the tx control u nit to do one l as t s hift, then de a ctiv a te s end a nd s et ti. thi s occ u r s a t the 11th divide- b y-16 rollover a fter ?write to s buf.? reception i s initi a ted b y a 1-to-0 tr a n s ition detected a t rxd. for thi s p u rpo s e, rxd i s sa mpled a t a r a te of 16 time s the e s t ab li s hed bau d r a te. when a tr a n s ition i s detected, the divide- b y-16 co u nter i s immedi a tely re s et, a nd 1ffh i s written to the inp u t s hift regi s ter. at the 7th, 8 th a nd 9th co u nter s t a te s of e a ch b it time, the b it detector sa mple s the v a l u e of rxd. the v a l u e a ccepted i s the v a l u e th a t w as s een in a t le as t 2 of the 3 sa mple s . if the v a l u e a ccepted d u ring the fir s t b it time i s not 0, the receive circ u it s a re re s et a nd the u nit contin u e s looking for a nother 1-to-0 tr a n s ition. if the s t a rt b it prove s v a lid, it i s s hifted into the inp u t s hift regi s ter, a nd reception of the re s t of the fr a me proceed s . a s d a t a b it s come in from the right, ?1? s s hift o u t to the left. when the s t a rt b it a rrive s a t the left- mo s t po s ition in the s hift regi s ter (which in mode s 2 a nd 3 i s a 9- b it regi s ter), it fl a g s the rx con- trol b lock to do one l as t s hift, lo a d s buf a nd rb 8 , a nd s et ri. the s ign a l to lo a d s buf a nd rb 8 a nd to s et ri i s gener a ted if, a nd only if, the fo llowing condition s a re met a t the time the fin a l s hift p u l s e i s gener a ted: ri = 0, a nd either s m2 = 0 or the received 9th d a t a b it = 1 if either of the s e condition s i s not met, the received fr a me i s irretriev ab ly lo s t, a nd ri i s not s et. if b oth condition s a re met, the received 9th d a t a b it goe s into rb 8 , a nd the fir s t 8 d a t a b it s go into s buf. one b it time l a ter, whether the ab ove condition s were met or not, the u nit contin u e s look- ing for a 1-to-0 tr a n s ition a t the rxd inp u t. note th a t the v a l u e of the received s top b it i s irrelev a nt to s buf, rb 8 , or ri.
71 3709c?micro?5/11 at89lp51/52 - preliminary figure 14-7. s eri a l port mode 2 s mod1 1 s mod1 0 internal bu s internal bu s cpu clock
72 3709c?micro?5/11 at89lp51/52 - preliminary figure 14-8. s eri a l port mode 3 tx clock write to s buf s end data s hift txd s top bit gen ti d0 d1 d2 d3 d4 d5 d6 d7 tb 8 s top bit tran s mit s tart bit internal bu s read s buf load s buf s buf s hift input s hift reg. (9 bit s ) bit detector 1-to-0 tran s ition detector s erial port interrupt write to s buf 2 s mod1 timer 1 overflow rxd rx clock rx clock rx control s ta rt s ta rt data s ample 16 16 tx control ti zero detector s buf txd internal bu s tb 8 d q cl s load s buf s hift 1ffh s hift ri s end d0 d1 d2 d3 d4 d5 d6 d7 rb 8 s tart bit s top bit 16 re s et rx clock bit detector s ample time s s hift receive rxd ri s top bit timer 2 overflow tclk rclk ?0? ?0? ?1? ?1? ?0? ?1?
73 3709c?micro?5/11 at89lp51/52 - preliminary 15. programmable watchdog timer the progr a mm ab le w a tchdog timer (wdt) protect s the s y s tem from incorrect exec u tion b y trig- gering a s y s tem re s et when it time s o u t a fter the s oftw a re h as f a iled to feed the timer prior to the timer overflow. by def au lt the wdt co u nt s cpu clock cycle s . the pre s c a ler b it s , p s 0, p s 1 a nd p s 2 in s fr wdtcon a re us ed to s et the period of the w a tchdog timer from 16k to 204 8 k clock cycle s . the timer pre s c a ler c a n a l s o b e us ed to lengthen the time-o u t period ( s ee t ab le 6-2 on p a ge 31 ) the wdt i s di sab led b y re s et a nd d u ring power-down mode. when the wdt time s o u t witho u t b eing s erviced, a n intern a l r s t p u l s e i s gener a ted to re s et the cpu. s ee t ab le 15-1 for the a v a il ab le wdt period s election s . note: 1. the wdt time-o u t period i s dependent on the s y s tem clock freq u ency. the w a tchdog timer con s i s t s of a 14- b it timer with 7- b it progr a mm ab le pre s c a ler. writing the s eq u ence 1eh/e1h to the wdtr s t regi s ter en ab le s the timer. when the wdt i s en ab led, the wdten b it in wdtcon will b e s et to ?1?. to prevent the wdt from gener a ting a re s et when if overflow s , the w a tchdog feed s eq u ence m us t b e written to wdtr s t b efore the end of the time- o u t period. to feed the w a tchdog, two write in s tr u ction s m us t b e s eq u enti a lly exec u ted su cce ss - f u lly. between the two write in s tr u ction s , s fr re a d s a re a llowed, bu t write s a re not a llowed. the in s tr u ction s s ho u ld move 1eh to the wdtr s t regi s ter a nd then 1eh to the wdtr s t regi s ter. an incorrect feed or en ab le s eq u ence will c aus e a n immedi a te w a tchdog re s et. the progr a m s eq u ence to feed or en ab le the w a tchdog timer i s as follow s : mov wdtr s t, #01eh mov wdtr s t, #0e1h 15.1 software reset a s oftw a re re s et of the at 8 9lp51/52 i s a ccompli s hed b y writing the s oftw a re re s et s eq u ence 5ah/a5h to the wdtr s t s fr. the wdt doe s not need to b e en ab led to gener a te the s oftw a re re s et. a norm a l s oftw a re re s et will s et the s wr s t fl a g in wdtcon. however, if a t a ny time a n incorrect s eq u ence i s written to wdtr s t (i.e. a nything other th a n 1eh/e1h or 5ah/a5h), a s oftw a re re s et will immedi a tely b e gener a ted a nd b oth the s wr s t a nd wdtovf fl a g s will b e s et. in thi s m a nner a n intention a l s oftw a re re s et m a y b e di s ting u i s hed from a s oftw a re error-gen- er a ted re s et. the progr a m s eq u ence to gener a te a s oftw a re re s et i s as follow s : table 15-1. w a tchdog timer time-o u t period s election wdt prescaler bits period (1) (clock cycles) ps2 ps1 ps0 000 16k 001 32k 010 64k 011 12 8 k 100 256k 101 512k 1 1 0 1024k 111 204 8 k time-o u t period 2 p s 14 + () s y s tem freq u ency ------------------------------------------------- - tp s 1 + () =
74 3709c?micro?5/11 at89lp51/52 - preliminary mov wdtr s t, #05ah mov wdtr s t, #0a5h note: 1. wdtcon.4 a nd wdtcon.3 f u nction as wdidle a nd di s rto only in f as t mode. in comp a ti b ility mode the s e b it s a re in auxr. ( s ee t ab le 3-3 on p a ge 20 ) table 15-2. wdtcon ? w a tchdog control regi s ter wdtcon addre ss = a7h re s et v a l u e = 0000 0xx0b not bit addre ssab le p s 2p s 1p s 0 wdidle (1) di s rto (1) s wr s t wdtovf wdten bit76543210 symbol function p s 2 p s 1 p s 0 pre s c a ler b it s for the w a tchdog timer (wdt). when a ll three b it s a re cle a red to 0, the w a tchdog timer h as a nomin a l period of 16k clock cycle s . when a ll three b it s a re s et to 1, the nomin a l period i s 204 8 k clock cycle s . wdidle wdt di sab le d u ring idle (1) . when wdidle = 0 the wdt contin u e s to co u nt in idle mode. when wdidle = 1 the wdt h a lt s co u nting in idle mode. di s rto di sab le re s et o u tp u t (1) . when di s tro = 0 the re s et pin i s driven to the sa me level as pol when the wdt re s et s . when di s rto = 1 the re s et pin i s inp u t only. s wr s t s oftw a re re s et fl a g. s et when a s oftw a re re s et i s gener a ted b y writing the s eq u ence 5ah/a5h to wdtr s t. a l s o s et when a n incorrect s eq u ence i s written to wdtr s t. m us t b e cle a red b y s oftw a re. wdtovf w a tchdog overflow fl a g. s et when a wdt re s t i s gener a ted b y the wdt timer overflow. al s o s et when a n incorrect s eq u ence i s written to wdtr s t. m us t b e cle a red b y s oftw a re. wdten w a tchdog en ab le fl a g. thi s b it i s read-only a nd reflect s the s t a t us of the wdt (whether it i s r u nning or not). the wdt i s di sab led a fter a ny re s et a nd m us t b e re-en ab led b y writing 1eh/e1h to wdtr s t table 15-3. wdtr s t ? w a tchdog re s et regi s ter wdtcon addre ss = a6h (write-only) not bit addre ssab le ???????? bit76543210 the wdt i s en ab led b y writing the s eq u ence 1eh/e1h to the wdtr s t s fr. the c u rrent s t a t us m a y b e checked b y re a ding the wdten b it in wdtcon. to prevent the wdt from re s etting the device, the sa me s eq u ence 1eh/e1h m us t b e written to wdtr s t b efore the time-o u t interv a l expire s . a s oftw a re re s et i s gener a ted b y writing the s eq u ence 5ah/a5h to wdtr s t.
75 3709c?micro?5/11 at89lp51/52 - preliminary 16. instruction set summary the at 8 9lp51/52 i s f u lly b in a ry comp a ti b le with the 8 051 in s tr u ction s et. in comp a ti b ility mode the at 8 9lp51/52 h as identic a l exec u tion time with at 8 9 s 51/52 a nd other s t a nd a rd 8 051 s . the difference b etween the at 8 9lp51/52 in f as t mode a nd the s t a nd a rd 8 051 i s the n u m b er of cycle s req u ired to exec u te a n in s tr u ction. f as t mode in s tr u ction s m a y t a ke 1 to 5 clock cycle s to complete. the exec u tion time s of mo s t in s tr u ction s m a y b e comp u ted us ing t ab le 16-1 . note th a t for the p u rpo s e s of thi s t ab le, a clock cycle i s one period of the o u tp u t of the s y s tem clock divider. for f as t mode the divider def au lt s to 1, s o the clock cycle eq ua l s the o s cill a tor period. for comp a ti b ility mode the divider def au lt s to 2, s o the clock cycle i s twice the o s cill a tor period, or conver s ely the clock co u nt i s h a lf the n u m b er of o s cill a tor period s . table 16-1. in s tr u ction exec u tion time s a nd exception s (1) generic instruction types fast mode cycle count formula mo s t a rithmetic, logic a l, b it a nd tr a n s fer in s tr u ction s # b yte s br a nche s a nd c a ll s # b yte s + 1 s ingle byte indirect (i.e. add a, @ri, etc.) 2 ret, reti 4 movc 3 movx 4 (3) mul 2 div 4 inc dptr 2 arithmetic bytes clock cycles hex code compatibility fast add a, rn 1 6 1 2 8 -2f add a, direct 2 6 2 25 add a, @ri 1 6 2 26-27 add a, #d a t a 26 2 24 addc a, rn 1 6 1 3 8 -3f addc a, direct 2 6 2 35 addc a, @ri 1 6 2 36-37 addc a, #d a t a 26 2 34 s ubb a, rn 1 6 1 9 8 -9f s ubb a, direct 2 6 2 95 s ubb a, @ri 1 6 2 96-97 s ubb a, #d a t a 26 2 94 inc rn 1 6 1 0 8 -0f inc direct 2 6 2 05 inc @ri 1 6 2 06-07 inc a 2 6 2 04 dec rn 1 6 1 1 8 -1f dec direct 2 6 2 15
76 3709c?micro?5/11 at89lp51/52 - preliminary dec @ri 1 6 2 16-17 dec a 2 6 2 14 inc dptr 1 12 2 a3 inc /dptr (2) 21 8 3a5 a3 mul ab 1 24 2 a4 div ab 1 24 4 8 4 da a 1 6 1 d4 logical bytes clock cycles hex code compatibility fast clr a 1 6 1 e4 cpl a 1 6 1 f4 anl a, rn 1 6 1 5 8 -5f anl a, direct 2 6 2 55 anl a, @ri 1 6 2 56-57 anl a, #d a t a 26 2 54 anl direct, a 2 6 2 52 anl direct, #d a t a 312 3 53 orl a, rn 1 6 1 4 8 -4f orl a, direct 2 6 2 45 orl a, @ri 1 6 2 46-47 orl a, #d a t a 26 2 44 orl direct, a 2 6 2 42 orl direct, #d a t a 312 3 43 xrl a, rn 1 6 1 6 8 -6f xrl a, direct 2 6 2 65 xrl a, @ri 1 6 2 66-67 xrl a, #d a t a 26 2 64 xrl direct, a 2 6 2 62 xrl direct, #d a t a 312 3 63 rl a 1 6 1 23 rlc a 1 6 1 33 rr a 1 6 1 03 rrc a 1 6 1 13 s wap a 1 6 1 c4 data transfer bytes clock cycles hex code compatibility fast mov a, rn 1 6 1 e 8 -ef mov a, direct 2 6 2 e5 mov a, @ri 1 6 2 e6-e7 table 16-1. in s tr u ction exec u tion time s a nd exception s (1) (contin u ed)
77 3709c?micro?5/11 at89lp51/52 - preliminary mov a, #d a t a 26 2 74 mov rn, a 1 6 1 f 8 -ff mov rn, direct 2 12 2 a 8 -af mov rn, #d a t a 26 27 8 -7f mov direct, a 2 6 2 f5 mov direct, rn 2 12 2 88 - 8 f mov direct, direct 3 12 3 8 5 mov direct, @ri 2 12 2 8 6- 8 7 mov direct, #d a t a 312 3 75 mov @ri, a 1 6 1 f6-f7 mov @ri, direct 2 12 2 a6-a7 mov @ri, #d a t a 2 6 2 76-77 mov dptr, #d a t a 16 3 12 3 90 mov /dptr, #d a t a 16 (2) 4? 4a5 90 movc a, @a+dptr 1 12 3 93 movc a, @a+/dptr (2) 2? 4a5 93 movc a, @a+pc 1 12 3 8 3 movx a, @ri 1 12 2 e2-e3 movx a, @dptr 1 12 (3) 4 (3) e0 movx a, @/dptr (2) 21 8 (3) 5 (3) a5 e0 movx @ri, a 1 12 2 f2-f3 movx @dptr, a 1 12 (3) 4 (3) f0 movx @/dptr, a (2) 21 8 (3) 5 (3) a5 f0 pu s h direct 2 12 2 c0 pop direct 2 12 2 d0 xch a, rn 1 6 1 c 8 -cf xch a, direct 2 6 2 c5 xch a, @ri 1 6 2 c6-c7 xchd a, @ri 1 6 2 d6-d7 bit operations bytes clock cycles hex code compatibility fast clr c 1 6 1 c3 clr b it 2 6 2 c2 s etb c 1 6 1 d3 s etb b it 2 6 2 d2 cpl c 1 6 1 b3 cpl b it 2 6 2 b2 anl c, b it 2 12 2 8 2 anl c, b it 2 12 2 b0 table 16-1. in s tr u ction exec u tion time s a nd exception s (1) (contin u ed)
78 3709c?micro?5/11 at89lp51/52 - preliminary note s : 1. a clock cycle i s one period of the o u tp u t of the s y s tem clock divider. for f as t mode the divider def au lt s to 1, s o the clock cycle eq ua l s the o s cill a tor period. for comp a ti b ility mode the divider def au lt s to 2, s o the clock cycle i s twice the o s cill a tor period, or conver s ely the clock co u nt i s h a lf the n u m b er of o s cill a tor period s . 2. thi s e s c a ped in s tr u ction i s a n exten s ion to the in s tr u ction s et. 3. thi s i s the minim u m time for movx with no w a it s t a te s . in comp a ti b ility mode a n a ddition a l 24 clock s a re a dded for the w a it s t a te. in f as t mode, 1 clock i s a dded for e a ch w a it s t a te (0?3). orl c, b it 2 12 2 72 orl c, / b it 2 12 2 a0 mov c, b it 2 6 2 a2 mov b it, c 2 12 2 92 branching bytes clock cycles hex code compatibility fast jc rel 2 12 3 40 jnc rel 2 12 3 50 jb b it, rel 3 12 4 20 jnb b it, rel 3 12 4 30 jbc b it, rel 3 12 4 10 jz rel 2 12 3 60 jnz rel 2 12 3 70 s jmp rel 2 12 3 8 0 acall a ddr11 2 12 3 11,31,51,71,91, b1,d1,f1 lcall a ddr16 3 12 4 12 ret 1 12 4 22 reti 1 12 4 32 ajmp a ddr11 2 12 3 01,21,41,61, 8 1, a1,c1,e1 ljmp a ddr16 3 12 4 02 jmp @a+dptr 1 12 2 73 jmp @a+pc (2) 212 3 a573 cjne a, direct, rel 3 12 4 b5 cjne a, #d a t a , rel 3 12 4 b4 cjne rn, #d a t a , rel 3 12 4 b 8 -bf cjne @ri, #d a t a , rel 3 12 4 b6-b7 cjne a, @r0, rel (2) 31 8 4a5 b6 cjne a, @r1, rel (2) 31 8 4a5 b7 djnz rn, rel 2 12 3 d 8 -df djnz direct, rel 3 12 4 d5 nop 1 6 1 00 table 16-1. in s tr u ction exec u tion time s a nd exception s (1) (contin u ed)
79 3709c?micro?5/11 at89lp51/52 - preliminary 17. programming the flash memory the atmel at 8 9lp51/52 microcontroller fe a t u re s 8 k b yte s of on-chip in- s y s tem progr a mm ab le fl as h progr a m memory a nd 256 b yte s of nonvol a tile fl as h d a t a memory. in- s y s tem progr a m- ming a llow s progr a mming a nd reprogr a mming of the microcontroller po s itioned in s ide the end s y s tem. u s ing a s imple 3-wire s pi interf a ce, the progr a mmer comm u nic a te s s eri a lly with the at 8 9lp51/52 microcontroller, reprogr a mming a ll nonvol a tile memorie s on the chip. in- s y s tem progr a mming elimin a te s the need for phy s ic a l remov a l of the chip s from the s y s tem. thi s will sa ve time a nd money, b oth d u ring development in the l ab , a nd when u pd a ting the s oftw a re or p a r a meter s in the field. the progr a mming interf a ce of the at 8 9lp51/52 incl u de s the following fe a t u re s : ? three-wire s eri a l s pi progr a mming interf a ce or 11-pin p a r a llel interf a ce ? s elect ab le pol a rity re s et entry into progr a mming ?u s er s ign a t u re arr a y ?flexi b le p a ge progr a mming ?row er as e c a p ab ility ?p a ge write with a u to-er as e comm a nd s ?progr a mming s t a t us regi s ter for more det a iled inform a tion on in- s y s tem progr a mming, refer to the applic a tion note entitled ?at 8 9lp in- s y s tem progr a mming s pecific a tion?. 17.1 physical interface the at 8 9lp51/52 provide s a s t a nd a rd progr a mming comm a nd s et with two phy s ic a l interf a ce s : a b it- s eri a l a nd a b yte-p a r a llel interf a ce. norm a l fl as h progr a mming u tilize s the s eri a l peripher a l interf a ce ( s pi) pin s of a n at 8 9lp51/52 microcontroller. the s pi i s a f u ll-d u plex s ynchrono us s eri a l interf a ce con s i s ting of three wire s : s eri a l clock ( s ck), m as ter-in/ s l a ve-o u t (mi s o), a nd m as ter-o u t/ s l a ve-in (mo s i)). when progr a mming a n at 8 9lp51/52 device, the progr a mmer a lw a y s oper a te s as the s pi m as ter, a nd the t a rget s y s tem a lw a y s oper a te s as the s pi s l a ve. to enter or rem a in in progr a mming mode the device? s re s et line (r s t) m us t b e held a ctive. with the a ddition of vdd a nd gnd, a n at 8 9lp51/52 microcontroller c a n b e progr a mmed with a min- im u m of s even connection s as s hown in fig u re 17-1 . figure 17-1. in- s y s tem progr a mming device connection s at 8 9lp51/52 vdd r s t p1.7/ s ck p1.5/mo s i gnd s eri a l clock s eri a l in r s t pol p1.6/mi s o s eri a l o u t gnd or vdd
80 3709c?micro?5/11 at89lp51/52 - preliminary the p a r a llel interf a ce i s a s peci a l mode of the s eri a l interf a ce, i.e. the s eri a l interf a ce i s us ed to en ab le the p a r a llel interf a ce. after en ab ling the interf a ce s eri a lly over p1.7/ s ck a nd p1.5/mo s i, p1.5 i s reconfig u red as a n a ctive-low o u tp u t en ab le (oe ) for d a t a on port 0. when oe =1, com- m a nd, a ddre ss a nd write d a t a b yte s a re inp u t on port 0 a nd sa mpled a t the ri s ing edge of s ck. when oe =0, re a d d a t a b yte s a re o u tp u t on port 0 a nd s ho u ld b e sa mpled on the f a lling edge of s ck. the p1.7/ s ck a nd r s t pin s contin u e to f u nction in the sa me m a nner. with the a ddition of vdd a nd gnd, the p a r a llel interf a ce req u ire s a minim u m of fo u rteen connection s as s hown in fig u re 17-2 . note th a t a connection to p1.6/mi s o i s not req u ired for us ing the p a r a llel interf a ce. figure 17-2. p a r a llel progr a mming device connection s the progr a mming interf a ce i s the only me a n s of extern a lly progr a mming the at 8 9lp51/52 microcontroller. the interf a ce c a n b e us ed to progr a m the device b oth in- s y s tem a nd in a s t a nd- a lone s eri a l progr a mmer. the interf a ce doe s not req u ire a ny clock other th a n s ck a nd i s not limited b y the s y s tem clock freq u ency. d u ring progr a mming the s y s tem clock s o u rce of the t a r- get device c a n oper a te norm a lly. when de s igning a s y s tem where in- s y s tem progr a mming will b e us ed, the following o bs erv a - tion s m us t b e con s idered for correct oper a tion: ?the i s p interf a ce us e s the s pi clock mode 0 (cpol = 0, cpha = 0) excl us ively with a m a xim u m freq u ency of 5 mhz. ?the at 8 9lp51/52 will enter progr a mming mode only when it s re s et line (r s t) i s a ctive. to s implify thi s oper a tion, it i s recommended th a t the t a rget re s et c a n b e controlled b y the in- s y s tem progr a mmer. to a void pro b lem s , the in- s y s tem progr a mmer s ho u ld b e ab le to keep the entire t a rget s y s tem re s et for the d u r a tion of the progr a mming cycle. the t a rget s y s tem s ho u ld never a ttempt to drive the three s pi line s while re s et i s a ctive. ?the i s p en ab le f us e m us t b e s et to a llow progr a mming d u ring a ny re s et period. if the i s p f us e i s di sab led, i s p m a y only b e entered a t por. to enter progr a mming the r s t pin m us t b e driven a ctive prior to the end of power-on re s et (por). after por h as completed the device will rem a in in i s p mode u ntil r s t i s b ro u ght in a ctive. once the initi a l i s p s e ss ion h as ended, the power to the t a rget device m us t b e cycled off a nd on to enter a nother s e ss ion. note th a t if thi s method i s req u ired, a n a ctive-low re s et pol a rity i s recommended. ?for s t a nd a lone progr a mmer s , a n a ctive-low re s et pol a rity i s recommended (pol = 0). r s t m a y then b e tied directly to gnd to en su re correct entry into progr a mming mode reg a rdle ss of the device s etting s . at 8 9lp51/52 vdd r s t p1.7/ s ck p1.5/mo s i gnd clock oe r s t pol gnd or vdd p0.7-0 d a t a in/o u t 8
81 3709c?micro?5/11 at89lp51/52 - preliminary 17.2 memory organization the at 8 9lp51/52 offer s 8 k b yte s of in- s y s tem progr a mm ab le (i s p) nonvol a tile fl as h code memory a nd 256 b yte s of nonvol a tile fl as h d a t a memory. in a ddition, the device cont a in s a 256- b yte u s er s ign a t u re arr a y a nd a 12 8 - b yte re a d-only atmel s ign a t u re arr a y. the memory org a ni- z a tion i s s hown in t ab le 17-1 a nd fig u re 17-3 . the memory i s divided into p a ge s of 12 8 b yte s e a ch. a s ingle re a d or write comm a nd m a y only a cce ss h a lf a p a ge (64 b yte s ) in the memory; however, write with au to-er as e comm a nd s will er as e a n entire 12 8 - b yte p a ge even tho u gh they c a n only write one h a lf p a ge. e a ch memory type re s ide s in it s own a ddre ss s p a ce a nd i s a cce ss ed b y comm a nd s s pecific to th a t memory. however, a ll memory type s s h a re the sa me p a ge s ize. u s er config u r a tion f us e s a re m a pped as a row in the memory, with e a ch b yte repre s enting one f us e. from a progr a mming s t a ndpoint, f us e s a re tre a ted the sa me as norm a l code b yte s except they a re not a ffected b y chip er as e. f us e s c a n b e en ab led a t a ny time b y writing 00h to the a ppropri a te loc a tion s in the f us e row. however, to di sab le a f us e, i.e. s et it to ffh, the entire f us e row m us t b e er as ed a nd then reprogr a mmed. the progr a mmer s ho u ld re a d the s t a te of a ll the f us e s into a tempor a ry loc a tion, modify tho s e f us e s which need to b e di sab led, then i ssu e a f us e write with a u to-er as e comm a nd us ing the tempor a ry d a t a . lock b it s a re tre a ted in a s imi- l a r m a nner to f us e s except they m a y only b e er as ed ( u nlocked) b y chip er as e. figure 17-3. at 8 9lp52 memory org a niz a tion table 17-1. at 8 9lp51/52 memory org a niz a tion memory capacity page size # pages address range code 4096 b yte s 8 192 b yte s 12 8 b yte s 32 64 0000h ? 0fffh 0000h ? 1fffh data 256 b yte s 12 8 b yte s 2 0000h ? 00ffh u s er s ign a t u re 256 b yte s 12 8 b yte s 2 0000h ? 00ffh atmel s ign a t u re 12 8 b yte s 12 8 b yte s 1 0000h ? 007fh page 6 3 low page 62 low user fuse row user signature array atmel signature array code memory 00 3 f 0000 1fff data memory page 6 3 high page 62 high 40 7f page 0 low page 0 low page 1 low page 0 high page 1 high page 0 low page 1 low page 0 low page 1 high page 1 high page 0 high 00 3 f page buffer page 0 low page 1 low page 0 high page 1 high
82 3709c?micro?5/11 at89lp51/52 - preliminary 17.3 command format progr a mming comm a nd s con s i s t of a n opcode b yte, two a ddre ss b yte s , a nd one or 64 d a t a b yte s . fig u re 17-4 on p a ge 8 2 s how s a s implified flow ch a rt of a comm a nd s eq u ence. a sa mple comm a nd p a cket i s s hown in fig u re 17-5 on p a ge 8 3 . the p a cket doe s not us e a chip s elect. comm a nd b yte s a re i ssu ed s eri a lly on mo s i. d a t a o u tp u t b yte s a re received s eri a lly on mi s o. the comm a nd i s not complete u ntil a ll b yte s h a ve b een tr a n s fered, incl u ding a ny don?t c a re b yte s . p a ge oriented in s tr u ction s a lw a y s incl u de a f u ll 16- b it a ddre ss . the higher order b it s s elect the p a ge a nd the lower order b it s s elect the b yte within th a t p a ge. the at 8 9lp51/52 a lloc a te s 6 b it s for b yte a ddre ss , 1 b it for low/high h a lf p a ge s election a nd 9 b it s for p a ge a ddre ss . the h a lf p a ge to b e a cce ss ed i s a lw a y s fixed b y the p a ge a ddre ss a nd h a lf s elect as tr a n s mitted. the b yte a ddre ss s pecifie s the s t a rting a ddre ss for the fir s t d a t a b yte. after e a ch d a t a b yte h as b een tr a n s mitted, the b yte a ddre ss i s incremented to point to the next d a t a b yte. thi s a llow s a p a ge comm a nd to line a rly s weep the b yte s within a p a ge. if the b yte a ddre ss i s incremented p as t the l as t b yte in the h a lf p a ge, the b yte a ddre ss will roll over to the fir s t b yte in the sa me h a lf p a ge. while lo a ding b yte s into the p a ge bu ffer, overwriting previo us ly lo a ded b yte s will re su lt in d a t a corr u ption. for a su mm a ry of a v a il ab le comm a nd s , s ee t ab le 17-2 on p a ge 8 4 . figure 17-4. comm a nd s eq u ence flow ch a rt inp u t opcode inp u t addre ss high byte inp u t addre ss low byte inp u t/o u tp u t d a t a addre ss +1 byte mode or co u nt == 64 ye s no
83 3709c?micro?5/11 at89lp51/52 - preliminary figure 17-5. i s p comm a nd p a cket ( s eri a l byte) figure 17-6. i s p comm a nd p a cket ( s eri a l p a ge) figure 17-7. i s p comm a nd p a cket (p a r a llel byte) figure 17-8. i s p comm a nd p a cket (p a r a llel p a ge) 70 654321 7 0 654321 7 0 654321 7 0 654321 70 654321 s ck mo s i mi s o opcode addre ss high addre ss low d a t a in d a t a o u t x x x 70 654321 7 0 654321 7 0 654321 7 0 654321 70 654321 s ck mo s i mi s o opcode addre ss high addre ss low d a t a in 0 d a t a o u t 0 x x x 70 654321 70 654321 d a t a in 63 d a t a o u t 63 s ck p0 opcode addre ss high addre ss low d a t a in oe write p0 opcode addre ss high addre ss low d a t a o u t oe read s ck p0 opcode addre ss high addre ss low d a t a in 0 oe write p0 opcode addre ss high addre ss low d a t a o u t 0 oe read d a t a in 63 d a t a o u t 63 o u t 62
84 3709c?micro?5/11 at89lp51/52 - preliminary note s :1.progr a m en ab le m us t b e the first comm a nd i ssu ed a fter entering into progr a mming mode. 2. 0110 1001b i s ret u rned on mi s o when progr a m en ab le w as su cce ss f u l. 3. p a r a llel en ab le s witche s the interf a ce from s eri a l to p a r a llel form a t u ntil r s t goe s in a ctive. 4. e a ch b yte a ddre ss s elect s one f us e or lock b it. d a t a b yte s m us t b e 00h or ffh. 5. s ee t ab le 17-5 on p a ge 8 6 for f us e definition s . 6. s ee t ab le 17-4 on p a ge 8 6 for lock bit definition s . table 17-2. progr a mming comm a nd su mm a ry command opcode addr high addr low data 0 data 1?63 progr a m en ab le (1) 1010 1100 0101 0011 xxxx xxxx xxxx xxxx (0110 1001) (2) ? p a r a llel en ab le (3) 1010 1100 0011 0101 xxxx xxxx xxxx xxxx ? chip er as e 1010 1100 100x xxxx xxxx xxxx xxxx xxxx ? re a d s t a t us 0110 0000 xxxx x xxx xxxx xxxx s t a t us o u t? write code byte 0100 0000 000 a aaaa asbb bbbb d a t a in ? re a d code byte 0010 0000 000 a aaaa asbb bbbb d a t a o u t? write code p a ge 0101 0000 000 a aaaa as 00 0000 byte 0 byte s 1?63 write code p a ge with a u to-er as e 0111 0000 000 a aaaa as 00 0000 byte 0 byte s 1?63 re a d code p a ge 0011 0000 000 a aaaa as 00 0000 byte 0 byte s 1?63 write d a t a byte 1100 0000 xxxx xxxx asbb bbbb d a t a in ? re a d d a t a byte 1010 0000 xxxx xxxx asbb bbbb d a t a o u t? write d a t a p a ge 1101 0000 xxxx xxxx as 00 0000 byte 0 byte s 1?63 write d a t a p a ge with a u to-er as e 1101 0010 xxxx xxxx as 00 0000 byte 0 byte s 1?63 re a d d a t a p a ge 1011 0000 xxxx xxxx as 00 0000 byte 0 byte s 1?63 write u s er f us e (5) 0100 0001 xxxx xxxx 00 bb bbbb f us e in (4) ? re a d u s er f us e (5) 0010 0001 xxxx xxxx 00 bb bbbb f us e o u t (4) ? write u s er f us e s (5) 0101 0001 xxxx xxxx 0000 0000 f us e 0 (4) byte s 1?63 write u s er f us e s with a u to-er as e (5) 0111 0001 xxxx xxxx 0000 0000 f us e 0 (4) f us e s 1?63 (4) re a d u s er f us e s (5) 0011 0001 xxxx xxxx 0000 0000 f us e 0 (4) f us e s 1?63 (4) write lock mode (6) 1010 1100 1110 00bb xxxx xxxx xxxx xxxx ? re a d lock mode (6) 0010 0100 xxxx xxxx xx xx xxxx xxxl llxx ? write lock bit (6) 0100 0100 xxxx xxxx 00 bb bbbb d a t a in (4) ? write lock bit s (6) 0101 0100 xxxx xxxx 0000 0000 byte 0 (4) byte s 1?63 (4) re a d lock bit s (6) 0011 0100 xxxx xxxx 0000 0000 byte 0 (4) byte s 1?63 (4) write u s er s ign a t u re byte 0100 0010 xxxx xxxx asbb bbbb d a t a in ? re a d u s er s ign a t u re byte 0010 0010 xxxx xxxx asbb bbbb d a t a o u t? write u s er s ign a t u re p a ge 0101 0010 xxxx xxxx as 00 0000 byte 0 byte 1?63 write u s er s ign a t u re p a ge with a u to-er as e 0111 0010 xxxx xxxx as 00 0000 byte 0 byte 1?63 re a d u s er s ign a t u re p a ge 0011 0010 xxxx xxxx as 00 0000 byte 0 byte 1?63 re a d atmel s ign a t u re byte (7) 0010 1000 xxxx xxxx 0 sbb bbbb d a t a o u t? re a d atmel s ign a t u re p a ge (7) 0011 1000 xxxx xxxx 0 s 00 0000 byte 0 byte 1?63
85 3709c?micro?5/11 at89lp51/52 - preliminary 7. atmel signature bytes : 8 . symbol key : 17.4 status register the c u rrent s t a te of the memory m a y b e a cce ss ed b y re a ding the s t a t us regi s ter. the s t a t us reg- i s ter i s s hown in t ab le 17-3 . 17.5 data polling the at 8 9lp51/52 implement s data polling to indic a te the end of a progr a mming cycle. while the device i s bus y, a ny a ttempted re a d of the l as t b yte written will ret u rn the d a t a b yte with the m s b complemented. once the progr a mming cycle h as completed, the tr u e v a l u e will b e a cce s - s i b le. d u ring er as e the d a t a i s assu med to b e ffh a nd data polling will ret u rn 7fh. when writing m u ltiple b yte s in a p a ge, the data v a l u e will b e the l as t d a t a b yte lo a ded b efore pro- gr a mming b egin s , not the written b yte with the highe s t phy s ic a l a ddre ss within the p a ge. 17.6 flash security the at 8 9lp51/52 provide s three lock bit s for fl as h code a nd d a t a memory s ec u rity. lock b it s c a n b e left u nprogr a mmed (ffh) or progr a mmed (00h) to o b t a in the protection level s li s ted in t ab le 17-4 . lock b it s c a n only b e er as ed ( s et to ffh) b y chip er as e. lock b it mode 2 di sab le s progr a mming of a ll memory s p a ce s , incl u ding the u s er s ign a t u re arr a y a nd u s er config u r a tion f us e s . u s er f us e s m us t b e progr a mmed b efore en ab ling lock b it mode 2 or 3. lock b it mode 3 addre ss : 0000h 0001h 0002h at 8 9lp51: 1eh 54h 05h at 8 9lp52: 1eh 54h 06h a :p a ge addre ss bit s :h a lf p a ge s elect bit b : byte addre ss bit x: don?t c a re bit table 17-3. s t a t us regi s ter ? ??? load s ucce ss wrtinh bu s y bit76543210 symbol function load lo a d fl a g. cle a red low b y the lo a d p a ge bu ffer comm a nd a nd s et high b y the next memory write. thi s fl a g s ign a l s th a t the p a ge bu ffer w as previo us ly lo a ded with d a t a b y the lo a d p a ge bu ffer comm a nd. s ucce ss su cce ss fl a g. cle a red low a t the s t a rt of a progr a mming cycle a nd will only b e s et high if the progr a mming cycle complete s witho u t interr u ption from the b rowno u t detector. wrtinh write inhi b it fl a g. cle a red low b y the b rowno u t detector (bod) whenever progr a mming i s inhi b ited d u e to v dd f a lling b elow the minim u m req u ired progr a mming volt a ge. if a bod epi s ode occ u r s d u ring progr a mming, the s ucce ss fl a g will rem a in low a fter the cycle i s complete. bu s y b us y fl a g. cle a red low whenever the memory i s bus y progr a mming or if write i s c u rrently inhi b ited.
86 3709c?micro?5/11 at89lp51/52 - preliminary implement s mode 2 a nd a l s o b lock s re a d s from the code a nd d a t a memorie s ; however, re a d s of the u s er s ign a t u re arr a y, atmel s ign a t u re arr a y, a nd u s er config u r a tion f us e s a re s till a llowed. the lock bit s will not di sab le fdata or iap progr a mming initi a ted b y the a pplic a tion s oftw a re. 17.7 user configuration fuses the at 8 9lp51/52 incl u de s 10 us er f us e s for config u r a tion of the device. e a ch f us e i s a cce ss ed a t a s ep a r a te a ddre ss in the u s er f us e row as li s ted in t ab le 17-5 . f us e s a re cle a red b y pro- gr a mming 00h to their loc a tion s . progr a mming ffh to a f us e loc a tion will c aus e th a t f us e to m a int a in it s previo us s t a te. to s et a f us e ( s et to ffh) the f us e row m us t b e er as ed a nd then reprogr a mmed us ing the f us e write with a u to-er as e comm a nd. the def au lt s t a te for a ll f us e s i s ffh except for tri s t a te port s , which def au lt s to 00h. table 17-4. lock bit protection mode s program lock bits (by address) mode 00h 01h 02h protection mode 1 ffh ffh ffh no progr a m lock fe a t u re s 200hffhffhf u rther progr a mming of the fl as h i s di sab led 300h00hffhf u rther progr a mming of the fl as h i s di sab led a nd verify (re a d) i s a l s o di sab led 4 00h 00h 00h f u rther progr a mming of the fl as h i s di sab led a nd verify (re a d) i s a l s o di sab led; extern a l exec u tion ab ove 4k/ 8 k i s di sab led table 17-5. u s er config u r a tion f us e definition s address fuse name description 00 ? 01h clock s o u rce ? c s [0:1] (2) s elect s s o u rce for the s y s tem clock: c s 1 c s 0 s elected s o u rce ffh ffh high s peed cry s t a l o s cill a tor (xtal) ffh 00h low s peed cry s t a l o s cill a tor (xtal) 00h ffh extern a l clock on xtal1 (xclk) 00h 00h intern a l a u xili a ry o s cill a tor (irc) 02 ? 03h s t a rt- u p time ? s ut[0:1] s elect s time-o u t del a y for the por/bod/pwd w a ke- u p period: s ut1 s ut0 s elected time-o u t 00h 00h 1 m s (xtal); 16 s (xclk/irc) 00h ffh 2 m s (xtal); 512 s (xclk/irc) ffh 00h 4 m s (xtal); 1 m s (xclk/irc) ffh ffh 16 m s (xtal); 4 m s (xclk/irc) 04h comp a ti b ility mode ffh: cpu f u nction s in 12-clock comp a ti b ility mode 00h: cpu f u nction s i s s ingle-cycle f as t mode 05h i s p en ab le (3) ffh: in- s y s tem progr a mming en ab led 00h: in- s y s tem progr a mming di sab led (en ab led a t por only) 06h u s er s ign a t u re progr a mming ffh: progr a mming of u s er s ign a t u re di sab led 00h: progr a mming of u s er s ign a t u re en ab led
87 3709c?micro?5/11 at89lp51/52 - preliminary note s : 1. the def au lt s t a te for tri s t a te port s i s 00h. all other f us e s def au lt to ffh. 2. ch a nge s to the s e f us e s will only t a ke effect a fter a device por. 3. ch a nge s to the s e f us e s will only t a ke effect a fter the i s p s e ss ion termin a te s b y b ringing r s t in a ctive. 17.8 user signature the u s er s ign a t u re arr a y cont a in s 256 b yte s of non-vol a tile memory in two 12 8 - b yte p a ge s . the u s er s ign a t u re i s a v a il ab le for s eri a l n u m b er s , firmw a re revi s ion inform a tion, d a te code s or other us er p a r a meter s . the u s er s ign a t u re arr a y m a y only b e written b y a n extern a l device when the u s er s ign a t u re progr a mming f us e i s en ab led. when the f us e i s en ab led, chip er as e will a l s o er as e the fir s t p a ge of the a rr a y. when the f us e i s di sab led, the a rr a y i s not a ffected b y write or er as e comm a nd s . progr a mming of the s ign a t u re arr a y c a n a l s o b e di sab led b y the lock bit s . however, re a ding the s ign a t u re i s a lw a y s a llowed a nd the a rr a y s ho u ld not b e us ed to s tore s ec u rity s en s itive inform a tion. the u s er s ign a t u re arr a y m a y b e modified d u ring exec u tion thro u gh the in-applic a tion progr a mming interf a ce, reg a rdle ss of the s t a te of the u s er s ign a t u re progr a mming f us e or lock bit s , provided th a t the iap f us e i s en ab led. note th a t the a ddre ss of the u s er s ign a t u re arr a y, as s een b y the iap interf a ce, eq ua l s the u s er s ign a t u re a ddre ss pl us 256 (0100h?01ffh in s te a d of 0000h?00ffh). 17.9 programming interface timing thi s s ection det a il s gener a l s y s tem timing s eq u ence s a nd con s tr a int s for entering or exiting in- s y s tem progr a mming as well as p a r a meter s rel a ted to the s eri a l peripher a l interf a ce d u ring i s p. the gener a l timing p a r a meter s for the following w a veform fig u re s a re li s ted in s ection ?tim- ing p a r a meter s ? on p a ge 91 . 17.9.1 power-up sequence exec u te thi s s eq u ence to enter progr a mming mode immedi a tely a fter power- u p. in the r s t pin i s di sab led or if the i s p f us e i s di sab led, thi s i s the only method to enter progr a mming ( s ee ?extern a l re s et? on p a ge 33 ). 1. apply power b etween vdd a nd gnd pin s . r s t s ho u ld rem a in low. 2. w a it a t le as t t pwrup . a nd drive r s t high if a ctive-high otherwi s e keep low. 3. w a it a t le as t t s ut for the intern a l power-on re s et to complete. the v a l u e of t s ut will depend on the c u rrent s etting s of the device. 4. s t a rt progr a mming s e ss ion. 07h tri s t a te port s ffh: i/o port s s t a rt in inp u t-only mode (tri s t a ted) a fter re s et 00h: i/o port s s t a rt in q uas i- b idirection a l mode a fter re s et 0 8 h in-applic a tion progr a mming ffh: in-applic a tion progr a mming di sab led 00h: in-applic a tion progr a mming en ab led 09h r1 en ab le ffh: 5 m re s i s tor on xtal1 di sab led 00h: 5 m re s i s tor on xtal1 en ab led table 17-5. u s er config u r a tion f us e definition s address fuse name description
88 3709c?micro?5/11 at89lp51/52 - preliminary figure 17-9. s eri a l progr a mming power- u p s eq u ence 17.9.2 power-down sequence exec u te thi s s eq u ence to power-down the device after progr a mming. 1. drive s ck low. 2. w a it a t le as t t ss d a nd tri s t a te mo s i. 3. w a it a t le as t t rhz a nd drive r s t low. 4. w a it a t le as t t ss z a nd tri s t a te s ck. 5. w a it no more th a n t pwrdn a nd power off vdd. figure 17-10. s eri a l progr a mming power-down s eq u ence 17.9.3 isp start sequence exec u te thi s s eq u ence to exit cpu exec u tion mode a nd enter i s p mode when the device h as p ass ed power-on re s et a nd i s a lre a dy oper a tion a l. 1. drive r s t high. 2. w a it t rlz + t s tl . 3. drive s ck low. 4. s t a rt progr a mming s e ss ion. v dd r s t r s t s ck high z mi s o high z mo s i t pwrup t por + t s ut v dd r s t s ck high z mi s o high z mo s i t pwrdn t ss d t ss z t rhz
89 3709c?micro?5/11 at89lp51/52 - preliminary figure 17-11. in- s y s tem progr a mming (i s p) s t a rt s eq u ence 17.9.4 isp exit sequence exec u te thi s s eq u ence to exit i s p mode a nd re su me cpu exec u tion mode. 1. drive s ck low. 1. w a it a t le as t t ss d . 2. tri s t a te mo s i. 3. w a it a t le as t t rhz a nd b ring r s t low. 4. w a it t ss z a nd tri s t a te s ck. figure 17-12. in- s y s tem progr a mming (i s p) exit s eq u ence note: the w a veform s on thi s p a ge a re not to s c a le. 17.9.5 serial peripheral interface the s eri a l peripher a l interf a ce ( s pi) i s a b yte-oriented f u ll-d u plex s ynchrono us s eri a l comm u ni- c a tion ch a nnel. d u ring in- s y s tem progr a mming, the progr a mmer a lw a y s a ct s as the s pi m as ter a nd the t a rget device a lw a y s a ct s as the s pi s l a ve. the t a rget device receive s s eri a l d a t a on mo s i a nd o u tp u t s s eri a l d a t a on mi s o. the progr a mming interf a ce implement s a s t a nd a rd s pi port with a fixed d a t a order a nd for in- s y s tem progr a mming, b yte s a re tr a n s ferred m s b fir s t as s hown in fig u re 17-13 . the s ck ph as e a nd pol a rity follow s pi clock mode 0 (cpol = 0, cpha = 0) where b it s a re sa mpled on the ri s ing edge of s ck a nd o u tp u t on the f a lling edge of s ck. for more det a iled timing inform a tion s ee fig u re 17-14 . t s tl v dd r s t s ck high z mo s i high z mi s o xtal1 t rlz t z ss t ss e v dd r s t s ck high z mo s i high z mi s o xtal1 t ss z t ss d t rhz
90 3709c?micro?5/11 at89lp51/52 - preliminary figure 17-13. i s p byte s eq u ence figure 17-14. s eri a l progr a mming interf a ce timing figure 17-15. p a r a llel progr a mming interf a ce timing 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 mo s i mi s o s ck d a t a sa mpled t sr t sse t slsh t sov t sf t sox t ssd t sck t shsl t soh t sih t sis rst sck miso mosi t sr t sse t slsh t sf t pox t ssd t sck t shsl t pov t poe t pih t pis rst sck p0 oe t poh
91 3709c?micro?5/11 at89lp51/52 - preliminary 17.9.6 timing parameters the timing p a r a meter s for fig u re 17-9 , fig u re 17-10 , fig u re 17-11 , fig u re 17-12 , fig u re 17-14 a nd fig u re 17-15 a re s hown in t ab le . note: 1. t s ck i s independent of t clcl . table 17-6. progr a mming interf a ce timing p a r a meter s symbol parameter min max units t clcl s y s tem clock cycle time 0 60 n s t pwrup power on to ss high time 10 s t por power-on re s et time 100 s t pwrdn ss tr i s t a te to power off 1 s t rlz r s t low to i/o tri s t a te t clcl 2 t clcl n s t s tl r s t low s ettling time 100 n s t rhz r s t high to ss tr i s t a te 0 2 t clcl n s t s ck s eri a l clock cycle time 200 (1) n s t s h s l clock high time 75 n s t s l s h clock low time 50 n s t s r ri s e time 25 n s t s f f a ll time 25 n s t s i s s eri a l inp u t s et u p time 10 n s t s ih s eri a l inp u t hold time 10 n s t s oh s eri a l o u tp u t hold time 10 n s t s ov s eri a l o u tp u t v a lid time 35 n s t pi s p a r a llel inp u t s et u p time 10 n s t pih p a r a llel inp u t hold time 10 n s t poh p a r a llel o u tp u t hold time 10 n s t pov p a r a llel o u tp u t v a lid time 35 n s t s oe s eri a l o u tp u t en ab le time 10 n s t s ox s eri a l o u tp u t di sab le time 25 n s t poe p a r a llel o u tp u t en ab le time 10 n s t pox p a r a llel o u tp u t di sab le time 25 n s t ss e r s t active le a d time t s l s h n s t ss d r s t in a ctive l a g time t s l s h n s t z ss s ck s et u p to ss low 25 n s t ss z s ck hold a fter ss high 25 n s t wr write cycle time 2.5 m s t awr write cycle with a u to-er as e time 5 m s t er s chip er as e cycle time 7.5 m s
92 3709c?micro?5/11 at89lp51/52 - preliminary 18. electrical characteristics note s : 1. under s te a dy s t a te (non-tr a n s ient) condition s , i ol m us t b e extern a lly limited as follow s : m a xim u m i ol per port pin: 10 ma m a xim u m tot a l i ol for a ll o u tp u t pin s : 100 ma if i ol exceed s the te s t condition, v ol m a y exceed the rel a ted s pecific a tion. pin s a re not g ua r a nteed to s ink c u rrent gre a ter th a n the li s ted te s t condition s . 2. minim u m v dd for power-down i s 2v. 3. all ch a r a cteri s tic s cont a ined in thi s d a t as heet a re bas ed on s im u l a tion a nd ch a r a cteriz a tion of other microcontroller s m a n u - f a ct u red in the sa me proce ss technology. the s e v a l u e s a re prelimin a ry v a l u e s repre s enting de s ign t a rget s , a nd will b e u pd a ted a fter ch a r a cteriz a tion of a ct ua l s ilicon. 18.1 absolute maximum ratings* oper a ting temper a t u re ................................... -40c to + 8 5c * notice: s tre ss e s b eyond tho s e li s ted u nder ?a bs ol u te m a xim u m r a ting s ? m a y c aus e perm a nent d a m- a ge to the device. thi s i s a s tre ss r a ting only a nd f u nction a l oper a tion of the device a t the s e or a ny other condition s b eyond tho s e indic a ted in the oper a tion a l s ection s of thi s s pecific a tion i s not implied. expo su re to abs ol u te m a xim u m r a ting condition s for extended period s m a y a ffect device reli ab ility. s tor a ge temper a t u re ..................................... -65c to +150c volt a ge on any pin with re s pect to gro u nd......-0.7v to +5.5v m a xim u m oper a ting volt a ge ............................................ 5.5v to t a l dc o u tp u t c u rrent ........................................... 150.0 ma 18.2 dc characteristics t a = -40c to 8 5c, v dd = 2.4v to 5.5v ( u nle ss otherwi s e noted) symbol parameter condition min max units v il inp u t low-volt a ge -0.5 0.2 v dd - 0.1 v v ih inp u t high-volt a ge 0.2 v dd + 0.9 v dd + 0.5 v v ol o u tp u t low-volt a ge (1) i ol = 10 ma, v dd = 2.4v, t a = 8 5c 0.5 v v oh o u tp u t high-volt a ge with we a k p u ll- u p s en ab led i oh = - 8 0 a, v dd = 3v 10% 2.4 v i oh = -30 a 0.75 v dd v i oh = -12 a 0.9 v dd v v oh1 o u tp u t high-volt a ge with s trong p u ll- u p s en ab led i oh = -10 ma, t a = 8 5c 0.9 v dd i oh = -5 ma, t a = 8 5c 0.75 v dd i il logic 0 inp u t c u rrent v in = 0.45v -50 a i tl logic 1 to 0 tr a n s ition c u rrent v in = 2v, v dd = 5v 10% -750 a i li inp u t le a k a ge c u rrent 0 < v in < v dd 10 a r r s t re s et p u ll- u p re s i s tor 50 150 k c io pin c a p a cit a nce te s t freq. = 1 mhz, t a = 25c 10 pf i cc power su pply c u rrent (f as t mode) active mode, 12 mhz, v dd = 5.5v 7 ma idle mode, 12 mhz, v dd = 5.5v 3 ma power su pply c u rrent (comp a ti b ility mode) active mode, 12 mhz, v dd = 5.5v 5 ma idle mode, 12 mhz, v dd = 5.5v 3 ma power-down mode (2) v dd = 5.5v 5 a v dd = 3v 2 a
93 3709c?micro?5/11 at89lp51/52 - preliminary 18.3 typical characteristics the following ch a rt s s how typic a l b eh a vior. the s e fig u re s a re not te s ted d u ring m a n u f a ct u ring. all c u rrent con su mption me asu rement s a re performed with a ll i/o pin s config u red as q uas i- b idi- rection a l (with intern a l p u ll- u p s ). a s q ua re w a ve gener a tor with r a il-to-r a il o u tp u t i s us ed as a n extern a l clock s o u rce for con su mption ver sus freq u ency me asu rement s . 18.3.1 supply current (internal oscillator) figure 18-1. active su pply c u rrent v s . vcc (1. 8 432 mhz intern a l o s cill a tor) 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.25 0.50 0.75 1.00 1.25 85c -40c 25c vcc (v) icc (ma) active supply current vs. vcc 1.8432 mhz internal oscillator compatibility mode 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.0 1.5 2.0 2.5 3.0 85c -40c 25c vcc (v) icc (ma) fast mode
94 3709c?micro?5/11 at89lp51/52 - preliminary figure 18-2. idle su pply c u rrent v s . vcc (1. 8 432 mhz intern a l o s cill a tor) note: all ch a r a cteri s tic s cont a ined in thi s d a t as heet a re bas ed on s im u l a tion a nd ch a r a cteriz a tion of other microcontroller s m a n u f a ct u red in the sa me proce ss technology. the s e v a l u e s a re prelimi- n a ry v a l u e s repre s enting de s ign t a rget s , a nd will b e u pd a ted a fter ch a r a cteriz a tion of a ct ua l s ilicon. 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.00 0.25 0.50 0.75 85c -40c 25c vcc (v) icc (ma) idle supply current vs. vcc 1.8432 mhz internal oscillator compatibility mode 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.00 0.25 0.50 0.75 85c -40c 25c vcc (v) icc (ma) fast mode
95 3709c?micro?5/11 at89lp51/52 - preliminary 18.3.2 supply current (external clock) figure 18-3. active su pply c u rrent v s . freq u ency 0 5 10 15 20 25 0 1 2 3 4 5 6 7 8 5.5v 5.0v 4.5v 3.6v 3.0v 2.4v frequency (mhz) icc (ma) active supply current vs. frequency external clock source compatibility mode 0 5 10 15 20 25 0 2 4 6 8 10 12 14 16 18 20 5.5v 5.0v 4.5v 3.6v 3.0v 2.4v frequency (mhz) icc (ma) fast mode 0 5 10 15 20 25 0 2 4 6 8 10 12 14 16 18 20 5v compat. 3v compat. 5v fast 3v fast mips icc (ma)
96 3709c?micro?5/11 at89lp51/52 - preliminary figure 18-4. idle su pply c u rrent v s . freq u ency 18.4 clock characteristics the v a l u e s s hown in thi s t ab le a re v a lid for t a = -40c to 8 5c a nd v dd = 2.4 to 5.5v, u nle ss otherwi s e noted. figure 18-5. extern a l clock drive w a veform 0 5 10 15 20 25 0.0 0.5 1.0 1.5 2.0 2.5 3.0 5.5v 5.0v 4.5v 3.6v 3.0v 2.4v frequency (mhz) icc (ma) idle supply current vs. frequency external clock source compatibility mode 0 5 10 15 20 25 0 1 2 3 4 5 6 5.5 v 5.0 v 4.5 v 3.6 v 3.0 v 2.4 v frequency (mhz) icc (ma) fast mode
97 3709c?micro?5/11 at89lp51/52 - preliminary note: 1. no w a it s t a te ( s ingle-cycle) fetch s peed for f as t mode 18.5 reset characteristics the v a l u e s s hown in thi s t ab le a re v a lid for t a = -40c to 8 5c a nd v dd = 2.4 to 5.5v, u nle ss otherwi s e noted. table 18-1. extern a l clock p a r a meter s symbol parameter v dd = 2.4v to 5.5v v dd = 4.5v to 5.5v units min max min max 1/t clcl o s cill a tor freq u ency (1) 020025mhz t clcl clock period 50 40 n s t chcx extern a l clock high time 12 n s t clcx extern a l clock low time 12 n s t clch extern a l clock ri s e time 5 n s t chcl extern a l clock f a ll time 5 n s table 18-2. clock ch a r a cteri s tic s symbol parameter condition min max units f xtal cry s t a l o s cill a tor freq u ency low power o s cill a tor 0 12 mhz high power o s cill a tor 0 24 mhz f rc intern a l o s cill a tor freq u ency t a = 25c; v dd = 5.0v 1. 8 24 1. 8 62 mhz v dd = 2.4 to 5.5v 1.751 1.935 mhz table 18-3. re s et ch a r a cteri s tic s symbol parameter condition min max units r r s t re s et p u ll- u p re s i s tor 50 150 k v por power-on re s et thre s hold 1.3 1.6 v v bod brown-o u t detector thre s hold 1.9 2.2 v v bh brown-o u t detector hy s tere s i s 200 300 mv t por power-on re s et del a y 135 150 s t wdtr s t w a tchdog re s et p u l s e width 49t clcl n s
98 3709c?micro?5/11 at89lp51/52 - preliminary 18.6 external memory characteristics the v a l u e s s hown in thi s t ab le a re v a lid for t a = -40c to 8 5c a nd v dd = 2.4 to 5.5v, u nle ss otherwi s e noted. under oper- a ting condition s , lo a d c a p a cit a nce for port 0, ale a nd p s en = 100 pf; lo a d c a p a cit a nce for a ll other o u tp u t s = 8 0 pf. p a r a meter s refer to fig u re 1 8 -6 , fig u re 1 8 -7 a nd fig u re 1 8 - 8 . note s :1.comp a ti b ility mode timing for movx a l s o a pplie s to f as t mode d u ring exetern a l exec u tion of movx. 2. thi s assu me s 50% clock d u ty cycle. the h a lf period depend s on the clock high v a l u e t chcx (high d u ty cycle). 3. thi s assu me s 50% clock d u ty cycle. the h a lf period depend s on the clock low v a l u e t clcx (low d u ty cycle). 4. in s ome c as e s p a r a meter t lhll m a y h a ve a minim u m of 0.5t clcl d u ring f as t mode extern a l exec u tion with di s ale = 0. 5. the s tro b e p u l s e width m a y b e lengthened b y 1, 2 or 3 a ddition a l t clcl us ing w a it s t a te s . table 18-4. extern a l progr a m a nd d a t a memory ch a r a cteri s tic s symbol parameter compatibility mode (1) fast mode (1) units min max min max 1/t clcl o s cill a tor freq u ency 024024mhz t lhll ale p u l s e width t clcl - d t clcl - d (4) n s t avll addre ss v a lid to ale low 0.5t clcl - d (2) 0.5t clcl - d (2) n s t llax addre ss hold a fter ale low 0.5t clcl - d (3) 0.5t clcl - d (3) n s t lliv ale low to v a lid in s tr u ction in 2t clcl - d 2t clcl - d n s t llpl ale low to p s en low 0.5t clcl - d (2) 0.5t clcl - d (2) n s t plph p s en p u l s e width 1.5t clcl - d (2) 1.5t clcl - d (2) n s t pliv p s en low to v a lid in s tr u ction in 1.5t clcl - d (2) 1.5t clcl - d (2) n s t pxix inp u t in s tr u ction hold a fter p s en 00n s t pxiz inp u t in s tr u ction flo a t a fter p s en 0.5t clcl - d (2) 0.5t clcl - d (2) n s t pxav p s en to addre ss v a lid 0.5t clcl - d (2) 0.5t clcl - d (2) n s t aviv addre ss to v a lid in s tr u ction in 2.5t clcl - d (2) 2.5t clcl - d (2) n s t plaz p s en low to addre ss flo a t1010n s t rlrh rd p u l s e width (5) 3t clcl - d t clcl - d n s t wlwh wr p u l s e width (5) 3t clcl - d t clcl - d n s t rldv rd low to v a lid d a t a in 2.5t clcl - d t clcl - d n s t rhdx d a t a hold a fter rd 00n s t rhdz d a t a flo a t a fter rd t clcl - d t clcl - d n s t lldv ale low to v a lid d a t a in 4t clcl - d 2t clcl - d n s t avdv addre ss to v a lid d a t a in 4.5t clcl - d (2) 2.5t clcl - d (2) n s t llwl ale low to rd or wr low 1.5t clcl - d 1.5t clcl + d t clcl - d t clcl + d n s t avwl addre ss to rd or wr low 2t clcl - d (2) 1.5t clcl - d (2) n s t qvwx d a t a v a lid to wr tr a n s ition 1t clcl - d (2) 0.5t clcl - d (2) n s t qvwh d a t a v a lid to wr high 4t clcl - d (2) 1.5t clcl - d (2) n s t whqx d a t a hold a fter wr 1t clcl - d (3) 0.5t clcl - d (3) n s t rlaz rd low to addre ss flo a t-1t clcl + d (2) -0.5t clcl + d (2) n s t whax addre ss hold a fter rd or wr high 1t clcl - d (3) 0.5t clcl - d (3) n s t whlh rd or wr high to ale high 0.5t clcl - d 0.5t clcl + d t clcl - d n s
99 3709c?micro?5/11 at89lp51/52 - preliminary figure 18-6. extern a l progr a m memory re a d cycle figure 18-7. extern a l d a t a memory re a d cycle figure 18-8. extern a l d a t a memory write cycle t lhll t lliv t pliv t llax t pxiz t plph t plaz t pxav t avll t llpl t aviv t pxix ale psen port 0 port 2 a8 - a15 a0 - a7 a0 - a7 a8 - a15 instr in t lhll ale data i n a0 - a7 a8 - a15 from dph or p2.0 - p2.7 p2 p2 rd port 0 port 2 t llwl t rlrh t avll t llax t rlaz t rhdz t avwl t whlh t whax t avdv t lldv t rldv t rhdx t lhll ale data out a0 - a7 a8 - a15 from dph or p2.0 - p2.7 p2 p2 wr port 0 port 2 t llwl t wlwh t avll t llax t qvwx t qvwh t whqx t avwl t whlh t whax
100 3709c?micro?5/11 at89lp51/52 - preliminary figure 18-9. s hift regi s ter mode timing w a veform 18.8 test conditions 18.8.1 ac testing input/output waveform (1) note: 1. ac inp u t s d u ring te s ting a re driven a t v dd - 0.5v for a logic ?1? a nd 0.45v for a logic ?0?. timing me asu rement s a re m a de a t v ih min. for a logic ?1? a nd v il m a x. for a logic ?0?. 18.7 serial port timing : shift register mode the v a l u e s in thi s t ab le a re v a lid for v dd = 2.4v to 5.5v a nd lo a d c a p a cit a nce = 8 0 pf. symbol parameter smod1 = 0 smod1 = 1 units min max min max t xlxl s eri a l port clock cycle time 4t clcl -15 2t clcl -15 s t qvxh o u tp u t d a t a s et u p to clock ri s ing edge 3t clcl -15 t clcl -15 n s t xhqx o u tp u t d a t a hold a fter clock ri s ing edge t clcl -15 t clcl -15 n s t xhdx inp u t d a t a hold a fter clock ri s ing edge 0 0 n s t xhdv inp u t d a t a v a lid to clock ri s ing edge 15 15 n s 01234567 v a lid v a lid v a lid v a lid v a lid v a lid v a lid v a lid clock write to s buf o u tp u t d a t a cle a r ri inp u t d a t a s mod1 = 0 01234567 v a lid v a lid v a lid v a lid v a lid v a lid v a lid v a lid clock write to s buf o u tp u t d a t a cle a r ri inp u t d a t a s mod1 = 1
101 3709c?micro?5/11 at89lp51/52 - preliminary 18.8.2 float waveform (1) note: 1. for timing p u rpo s e s , a port pin i s no longer flo a ting when a 100 mv ch a nge from lo a d volt a ge occ u r s . a port pin b egin s to flo a t when 100 mv ch a nge from the lo a ded v oh /v ol level occ u r s . 18.8.3 i cc test condition, active mode , all other pins are disconnected 18.8.4 i cc test condition, idle mode, all other pins are disconnected 18.8.5 clock signal waveform for i cc tests in active and idle modes, t clch = t chcl = 5 ns x t al 2 rst v dd v dd i cc x t al 1 gnd (nc) clock signal v dd pol gnd x t al 2 rst v dd v dd i cc x t al 1 gnd (nc) clock signal v dd gnd pol v cc - 0.5v 0.45v 0.2 v cc - 0.1v 0.7 v cc t chcx t chcx t clch t chcl t clcl
102 3709c?micro?5/11 at89lp51/52 - preliminary 18.8.6 i cc test condition, power-down mode, all other pins are disconnected, v dd = 2v to 5.5v xtal2 rst v dd v dd i cc xtal1 gnd (nc) v dd pol gnd
103 3709c?micro?5/11 at89lp51/52 - preliminary 19. ordering information 19.1 green package op tion (pb/halide-free) speed (mhz) power supply code memory ordering code package operation range 20 2.4v to 5.5v 4kb at 8 9lp51-20au at 8 9lp51-20pu at 8 9lp51-20ju at 8 9lp51-20mu 44a 40p6 44j 44m1 ind us tri a l (-40 c to 8 5 c) 20 2.4v to 5.5v 8 kb at 8 9lp52-20au at 8 9lp52-20pu at 8 9lp52-20ju at 8 9lp52-20mu 44a 40p6 44j 44m1 ind us tri a l (-40 c to 8 5 c) package types 44a 44-le a d, thin pl as tic q ua d fl a t p a ck a ge (tqfp) 40p6 40-le a d, 0.600? wide, pl as tic d ua l inline p a ck a ge (pdip) 44j 44-le a d, pl as tic j-le a ded chip c a rrier (plcc) 44m1 44-p a d, 7 x 7 x 1.0 mm body, pl as tic very thin q ua d fl a t no le a d p a ck a ge (vqfn/mlf)
104 3709c?micro?5/11 at89lp51/52 - preliminary 20. packaging information 20.1 44a ? tqfp 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 44a, 44-lead, 10 x 10 mm body size, 1.0 mm body thickness, 0.8 mm lead pitch, thin profile plastic quad flat package (tqfp) b 44a 10/5/2001 pin 1 identifier 0?~7? pin 1 l c a1 a2 a d1 d e e1 e b common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference ms-026, variation acb. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.10 mm maximum. a 1.20 a1 0.05 0.15 a2 0.95 1.00 1.05 d 11.75 12.00 12.25 d1 9.90 10.00 10.10 note 2 e 11.75 12.00 12.25 e1 9.90 10.00 10.10 note 2 b 0.30 0.45 c 0.09 0.20 l 0.45 0.75 e 0.80 typ
105 3709c?micro?5/11 at89lp51/52 - preliminary 20.2 40p6 ? pdip 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 40p6 , 40-lead (0.600"/15.24 mm wide) plastic dual inline package (pdip) b 40p6 09/28/01 pin 1 e1 a1 b ref e b1 c l seating plane a 0?~ 15? d e eb common dimensions (unit of measure = mm) symbol min nom max note a 4.826 a1 0.381 d 52.070 52.578 note 2 e 15.240 15.875 e1 13.462 13.970 note 2 b 0.356 0.559 b1 1.041 1.651 l 3.048 3.556 c 0.203 0.381 eb 15.494 17.526 e 2.540 typ notes: 1. this package conforms to jedec reference ms-011, variation ac. 2. dimensions d and e1 do not include mold flash or protrusion. mold flash or protrusion shall not exceed 0.25 mm (0.010").
106 3709c?micro?5/11 at89lp51/52 - preliminary 20.3 44j ? plcc note s : 1. thi s p a ck a ge conform s to jedec reference m s -01 8 , v a ri a tion ac. 2. dimen s ion s d1 a nd e1 do not incl u de mold protr us ion. allow ab le protr us ion i s .010"(0.254 mm) per s ide. dimen s ion d1 a nd e1 incl u de mold mi s m a tch a nd a re me asu red a t the extreme m a teri a l condition a t the u pper or lower p a rting line. 3. le a d copl a n a rity i s 0.004" (0.102 mm) m a xim u m. a 4.191 ? 4.572 a1 2.2 8 6 ? 3.04 8 a2 0.50 8 ? ? d 17.399 ? 17.653 d1 16.510 ? 16.662 note 2 e 17.399 ? 17.653 e1 16.510 ? 16.662 note 2 d2/e2 14.9 8 6 ? 16.002 b 0.660 ? 0. 8 13 b1 0.330 ? 0.533 e 1.270 typ common dimensions (unit of me asu re = mm) symbol min nom max note 1.14(0.045) x 45? pin no. 1 identifier 1.14(0.045) x 45? 0.51(0.020)max 0.31 8 (0.0125) 0.191(0.0075) a2 45? max (3x) a a1 b1 d2/e2 b e e1 e d1 d 44j , 44-le a d, pl as tic j-le a ded chip c a rrier (plcc) b 44j 10/04/01 2325 orch a rd p a rkw a y sa n jo s e, ca 95131 title drawing no. r rev.
107 3709c?micro?5/11 at89lp51/52 - preliminary 20.4 44m1 ? vqfn/mlf title drawing no. gpc rev. packa g e drawin g contact: packagedrawings@atmel.com 44m1 zws h 44m1, 44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, 5.20 mm exposed pad, thermally enhanced plastic very thin quad flat no lead package (vqfn) 9/26/08 common dimen s ion s (unit of measure = mm) s ymbol min nom max note a 0.80 0.90 1.00 a1 ? 0.02 0.05 a 3 0.20 ref b 0.18 0.2 3 0. 3 0 d d2 5.00 5.20 5.40 6.90 7.00 7.10 6.90 7.00 7.10 e e2 5.00 5.20 5.40 e 0.50 bsc l 0.59 0.64 0.69 k 0.20 0.26 0.41 note: jedec standard mo-220, fig. 1 (saw singulation) vkkd- 3 . top view s ide view bottom view d e marked pin# 1 id e2 d2 b e pin #1 corner l a1 a 3 a seating plane pin #1 triangle pin #1 chamfer (c 0. 3 0) option a option b pin #1 notch (0.20 r) option c k k 1 2 3
108 3709c?micro?5/11 at89lp51/52 - preliminary 21. revision history revision no. history revi s ion a ? s ept. 2010 ? initi a l rele as e revi s ion b ? dec. 2010 ? added at 8 9lp51 device ? upd a ted device id s ? lowered minim u m oper a ting volt a ge to 2.4v revi s ion c ? m a y 2011 ? added s y s tem config u r a tion ( s ection 2.2 on p a ge 7 ) ? added code s ize to ordering t ab le
i 3709c?micro?5/11 at89lp51/52 - preliminary table of contents features ................ ................ .............. ............... .............. .............. ............ 1 1 pin configurations ..... ................ ................. ................ ................. ............ 2 1.1 40-le a d pdip .....................................................................................................2 1.2 44-le a d tqfp ....................................................................................................2 ................... ................. ................ ................ ................. ................ ............... 3 1.3 44-le a d plcc ....................................................................................................3 1.4 44-p a d vqfn/qfn/mlf ....................................................................................3 1.5 pin de s cription ..................................................................................................4 2 overview ............ ................ ................ ............... .............. .............. ............ 6 2.1 block di a gr a m ...................................................................................................7 2.2 s y s tem config u r a tion ........................................................................................7 2.3 comp a ri s on to at 8 9 s 51/52 .............................................................................. 8 3 memory organization ......... .............. ............... .............. .............. .......... 11 3.1 progr a m memory .............................................................................................11 3.2 intern a l d a t a memory ......................................................................................14 3.3 extern a l d a t a memory .....................................................................................14 3.4 in-applic a tion progr a mming (iap) ...................................................................23 4 special function registers ..... ................ ................. ................ ............. 24 5 enhanced cpu ............. ................. ................ ................. .............. .......... 25 5.1 f as t mode ........................................................................................................25 5.2 comp a ti b ility mode ..........................................................................................26 5.3 enh a nced d ua l d a t a pointer s .........................................................................26 6 system clock ............. ................ ................. ................ ................. .......... 29 6.1 cry s t a l o s cill a tor .............................................................................................29 6.2 extern a l clock s o u rce .....................................................................................30 6.3 intern a l rc o s cill a tor ......................................................................................30 6.4 s y s tem clock divider ......................................................................................31 7 reset ............. ................ ................. ................ ................. .............. .......... 32 7.1 power-on re s et ...............................................................................................32 7.2 brown-o u t re s et ..............................................................................................33 7.3 extern a l re s et .................................................................................................33 7.4 w a tchdog re s et ..............................................................................................34
ii 3709c?micro?5/11 at89lp51/52 - preliminary table of contents (continued) 7.5 s oftw a re re s et ................................................................................................34 8 power saving modes .......... .............. ............... .............. .............. .......... 34 8 .1 idle mode .........................................................................................................34 8 .2 power-down mode ...........................................................................................35 8 .3 red u cing power con su mption ........................................................................37 9 interrupts ........ ................. ................ ................. .............. .............. .......... 37 9.1 interr u pt re s pon s e time .................................................................................3 8 10 i/o ports ............... ................ .............. ............... .............. .............. .......... 41 10.1 port config u r a tion ............................................................................................41 10.2 port re a d-modify-write ...................................................................................44 10.3 port altern a te f u nction s ..................................................................................45 11 timer 0 and timer 1 ............ .............. ............... .............. .............. .......... 46 11.1 mode 0 ? 13- b it timer/co u nter ........................................................................47 11.2 mode 1 ? 16- b it timer/co u nter ........................................................................47 11.3 mode 2 ? 8 - b it a u to-relo a d timer/co u nter .....................................................4 8 11.4 mode 3 ? 8 - b it s plit timer ...............................................................................4 8 11.5 clock o u tp u t (pin toggle mode) .....................................................................49 12 timer 2 ................. ................ .............. ............... .............. .............. .......... 51 12.1 timer 2 regi s ter s ............................................................................................52 12.2 c a pt u re mode ..................................................................................................53 12.3 a u to-relo a d mode ...........................................................................................53 12.4 b au d r a te gener a tor ......................................................................................55 12.5 freq u ency gener a tor (progr a mm ab le clock o u t) ...........................................56 13 external interrupts .......... ................ ................. .............. .............. .......... 57 14 serial interface (uart) .............. ................. ................ ................. .......... 57 14.1 m u ltiproce ss or comm u nic a tion s .....................................................................59 14.2 b au d r a te s ......................................................................................................59 14.3 fr a ming error detection ..................................................................................61 14.4 a u tom a tic addre ss recognition ......................................................................61 14.5 more a b o u t mode 0 .........................................................................................63 14.6 more a b o u t mode 1 .........................................................................................6 8 14.7 more a b o u t mode s 2 a nd 3 .............................................................................70
iii 3709c?micro?5/11 at89lp51/52 - preliminary table of contents (continued) 15 programmable watchdog timer .. ................ ................. .............. .......... 73 15.1 s oftw a re re s et ................................................................................................73 16 instruction set summary ... .............. ............... .............. .............. .......... 75 17 programming the flash memory .................... .............. .............. .......... 79 17.1 phy s ic a l interf a ce ............................................................................................79 17.2 memory org a niz a tion ...................................................................................... 8 1 17.3 comm a nd form a t ............................................................................................ 8 2 17.4 s t a t us regi s ter ................................................................................................ 8 5 17.5 data polling ................................................................................................... 8 5 17.6 fl as h s ec u rity .................................................................................................. 8 5 17.7 u s er config u r a tion f us e s ................................................................................ 8 6 17. 8 u s er s ign a t u re ................................................................................................. 8 7 17.9 progr a mming interf a ce timing ........................................................................ 8 7 18 electrical characteristics ... .............. ............... .............. .............. .......... 92 1 8 .1 a bs ol u te m a xim u m r a ting s* ...........................................................................92 1 8 .2 dc ch a r a cteri s tic s ...........................................................................................92 1 8 .3 typic a l ch a r a cteri s tic s ....................................................................................93 1 8 .4 clock ch a r a cteri s tic s .......................................................................................96 1 8 .5 re s et ch a r a cteri s tic s ......................................................................................97 1 8 .6 extern a l memory ch a r a cteri s tic s .....................................................................9 8 1 8 .7 s eri a l port timing: s hift regi s ter mode ........................................................100 1 8 . 8 te s t condition s ..............................................................................................100 19 ordering information .......... .............. ............... .............. .............. ........ 103 19.1 green p a ck a ge option (p b /h a lide-free) ........................................................103 20 packaging information .......... ................ ................. ................ ............. 104 20.1 44a ? tqfp ...................................................................................................104 20.2 40p6 ? pdip ..................................................................................................105 20.3 44j ? plcc ...................................................................................................106 20.4 44m1 ? vqfn/mlf .......................................................................................107 21 revision history ....... ................ ................ ................. ................ ........... 108
iv 3709c?micro?5/11 at89lp51/52 - preliminary
3709c?micro?5/11 atmel corporation 2325 orch a rd p a rkw a y sa n jo s e, ca 95131 u s a tel : (+1) (40 8 ) 441-0311 fax : (+1) (40 8 ) 4 8 7-2600 www. a tmel.com 8 051@ a tmel.com atmel asia limited unit 1-5 & 16, 19/f bea tower, millenni u m city 5 41 8 kw u n tong ro a d kw u n tong, kowloon hong kong tel : (+ 8 52) 2245-6100 fax : (+ 8 52) 2722-1369 atmel munich gmbh b us ine ss c a mp us p a rkring 4 d- 8 574 8 g a rching b . m u nich germany tel : (+49) 8 9-31970-0 fax : (+49) 8 9-3194621 atmel japan 9f, tonet su s hink a w a bldg. 1-24- 8 s hink a w a ch u o-k u , tokyo 104-0033 japan tel : (+ 8 1) (3) 3523-3551 fax : (+ 8 1) (3) 3523-75 8 1 disclaimer: the inform a tion in thi s doc u ment i s provided in connection with atmel prod u ct s . no licen s e, expre ss or implied, b y e s toppel or otherwi s e, to a ny intellect ua l property right i s gr a nted b y thi s doc u ment or in connection with the sa le of atmel prod u ct s . except as set forth in atmel?s terms and condi- tions of sale located on atmel?s web site, atmel assumes no li ability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, consequential, punitive, special or i nciden- tal damages (including, without limitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atme l has been advised of the possibility of such damages. atmel m a ke s no repre s ent a tion s or w a rr a ntie s with re s pect to the a cc u r a cy or completene ss of the content s of thi s doc u ment a nd re s erve s the right to m a ke ch a nge s to s pecific a tion s a nd prod u ct de s cription s a t a ny time witho u t notice. atmel doe s not m a ke a ny commitment to u pd a te the inform a tion cont a ined herein. unle ss s pecific a lly provided otherwi s e, atmel prod u ct s a re not su it ab le for, a nd s h a ll not b e us ed in, au tomotive a pplic a tion s . atmel? s prod u ct s a re not intended, au thorized, or w a rr a nted for us e as component s in a pplic a tion s intended to su pport or sus t a in life. ? 2010 atmel corporation. all rights reserved. atmel ? , atmel logo a nd com b in a tion s thereof, a nd other s a re regi s tered tr a dem a rk s or tr a de- m a rk s of atmel corpor a tion or it s subs idi a rie s . other term s a nd prod u ct n a me s m a y b e tr a dem a rk s of other s .

▲Up To Search▲

Price & Availability of AT89LP52-20AU

	To Download AT89LP52-20AU Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .